From c62601bf3d7cebdc480c2127a95c7d4db72e2089 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Thu, 22 Jun 2023 11:30:41 +0100 Subject: [PATCH] Distributed filelists to appropriate repositories --- flist/ahb/ahb_ip.flist | 8 ++--- flist/ahb/ahb_vip.flist | 7 +++-- flist/apb/apb_ip.flist | 9 ++---- flist/corstone-101/corstone-101_ip.flist | 36 ----------------------- flist/corstone-101/corstone-101_vip.flist | 25 ---------------- flist/cortex-m0/cortex-m0_ip.flist | 31 ------------------- flist/dma-230/pl230_ip.flist | 26 ---------------- flist/primitives/primitives.flist | 3 -- flist/project/system.flist | 11 +------ flist/project/wrapper.flist | 2 -- flist/wrapper/wrapper_ip.flist | 4 --- nanosoc_tech | 2 +- 12 files changed, 12 insertions(+), 152 deletions(-) delete mode 100644 flist/corstone-101/corstone-101_ip.flist delete mode 100644 flist/corstone-101/corstone-101_vip.flist delete mode 100644 flist/cortex-m0/cortex-m0_ip.flist delete mode 100644 flist/dma-230/pl230_ip.flist diff --git a/flist/ahb/ahb_ip.flist b/flist/ahb/ahb_ip.flist index cc09e57..99ae333 100644 --- a/flist/ahb/ahb_ip.flist +++ b/flist/ahb/ahb_ip.flist @@ -16,8 +16,8 @@ +libext+.v+.vlib // ============= Accelerator Module search path ============= -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog +// CMSDK AHB Slave Mux IP +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog \ No newline at end of file +// CMSDK AHB Default Slave IP +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v \ No newline at end of file diff --git a/flist/ahb/ahb_vip.flist b/flist/ahb/ahb_vip.flist index 86e67d2..0dc7b67 100644 --- a/flist/ahb/ahb_vip.flist +++ b/flist/ahb/ahb_vip.flist @@ -16,6 +16,7 @@ +libext+.v+.vlib // ============= Accelerator Module search path ============= -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog - --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v +$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v diff --git a/flist/apb/apb_ip.flist b/flist/apb/apb_ip.flist index 24e608f..cd12720 100644 --- a/flist/apb/apb_ip.flist +++ b/flist/apb/apb_ip.flist @@ -1,5 +1,5 @@ //----------------------------------------------------------------------------- -// Accelerator Wrapper CMSDK Filelist +// CMSDK APB IP Filelist // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // // Contributors @@ -15,12 +15,7 @@ // ============= Verilog library extensions =========== +libext+.v+.vlib -// ============= Accelerator Module search path ============= --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog - +// ============= CMSDK APB IP search path ============= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v diff --git a/flist/corstone-101/corstone-101_ip.flist b/flist/corstone-101/corstone-101_ip.flist deleted file mode 100644 index 60800f6..0000000 --- a/flist/corstone-101/corstone-101_ip.flist +++ /dev/null @@ -1,36 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Corstone-101 Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for Arm Corstone-101 -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= Corstone-101 search path ============= -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ - --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog \ No newline at end of file diff --git a/flist/corstone-101/corstone-101_vip.flist b/flist/corstone-101/corstone-101_vip.flist deleted file mode 100644 index 1c64fa5..0000000 --- a/flist/corstone-101/corstone-101_vip.flist +++ /dev/null @@ -1,25 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Corstone-101 VIP Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for Arm Corstone-101 VIP -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= DMA-230 search path ============= -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog - --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog \ No newline at end of file diff --git a/flist/cortex-m0/cortex-m0_ip.flist b/flist/cortex-m0/cortex-m0_ip.flist deleted file mode 100644 index 49a5afa..0000000 --- a/flist/cortex-m0/cortex-m0_ip.flist +++ /dev/null @@ -1,31 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC Cortex-M0 Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for Arm Cortex-M0 -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= Accelerator Module search path ============= --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers --y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog - -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers -+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog diff --git a/flist/dma-230/pl230_ip.flist b/flist/dma-230/pl230_ip.flist deleted file mode 100644 index 8c862a5..0000000 --- a/flist/dma-230/pl230_ip.flist +++ /dev/null @@ -1,26 +0,0 @@ -//----------------------------------------------------------------------------- -// NanoSoC DMA-230 Filelist -// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. -// -// Contributors -// -// David Mapstone (d.a.mapstone@soton.ac.uk) -// -// Copyright � 2021-3, SoC Labs (www.soclabs.org) -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -// Abstract : Verilog Command File for Arm DMA-230 -//----------------------------------------------------------------------------- - -// ============= Verilog library extensions =========== -+libext+.v+.vlib - -// ============= DMA-230 search path ============= -+incdir+$(SOCLABS_PROJECT_DIR)/system/defines/pl230 - -$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v -$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v -$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v -$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v -$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v - diff --git a/flist/primitives/primitives.flist b/flist/primitives/primitives.flist index bb0e871..30a7272 100644 --- a/flist/primitives/primitives.flist +++ b/flist/primitives/primitives.flist @@ -16,7 +16,4 @@ +libext+.v+.vlib // ============= RTL Primitives search path ============= --y $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/ -+incdir+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/ - $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv diff --git a/flist/project/system.flist b/flist/project/system.flist index 10765af..5c53c0f 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -43,16 +43,7 @@ -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist // - CMSDK VIP --f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist - -// - Corstone-101 System components --f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist - -// - DMA controller --f $(SOCLABS_PROJECT_DIR)/flist/dma-230/pl230_ip.flist - -// - Cortex-M0 IP --f $(SOCLABS_PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist // - NanoSoC Custom Expansion Region //$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v diff --git a/flist/project/wrapper.flist b/flist/project/wrapper.flist index f553705..0c715b2 100644 --- a/flist/project/wrapper.flist +++ b/flist/project/wrapper.flist @@ -21,8 +21,6 @@ -f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist // ============= Accelerator Module search path ============= --y $(SOCLABS_PROJECT_DIR)/wrapper/src/ -+incdir+$(SOCLABS_PROJECT_DIR)/wrapper/src/ // Add the source files related to your custom wrapper // $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v diff --git a/flist/wrapper/wrapper_ip.flist b/flist/wrapper/wrapper_ip.flist index 1e406b8..f41d660 100644 --- a/flist/wrapper/wrapper_ip.flist +++ b/flist/wrapper/wrapper_ip.flist @@ -16,12 +16,8 @@ +libext+.v+.vlib // ============= Accelerator Module search path ============= --y $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/ -+incdir+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/ - $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv - $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv diff --git a/nanosoc_tech b/nanosoc_tech index 226b723..d0ddcf0 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit 226b723d27c500624446478a2303588500b3eddd +Subproject commit d0ddcf03185befc43936756573f3bc4aa7d496b1 -- GitLab