SOC1-167: Updated filelist and modified system simulation script

flist/corstone-101/corstone-101_ip.flist

@@ -15,7 +15,7 @@
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    DMA-230 search path    =============
+// =============    Corstone-101 search path    =============
 +incdir+$(PROJECT_DIR)/system/defines/corstone101
 
 +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog

flist/nanosoc/nanosoc_chip_ip.flist

@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip_pads.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_chip.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_chip_pads.v
 
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_cpu.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sysio.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_cpu.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_sysio.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_sys_ahb_decode.v
 
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_ahb_cs_rom_table.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_pin_mux.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_stclkctrl.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_clkctrl.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_sysctrl.v
 
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/bootrom.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ahb_bootrom.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/bootrom.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ahb_bootrom.v
\ No newline at end of file

flist/nanosoc/nanosoc_matrix_ip.flist

@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
++incdir+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
 
--y $(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
\ No newline at end of file
+-y $(NANOSOC_TECH_DIR)/systems/nanososc/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    DMA-230 search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/
++incdir+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/
 
 // - Top-level testbench
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/tb_nanosoc.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/tb_nanosoc.v
 
 // - Testbench components
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_clkreset.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_uart_capture.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_txd_from_file.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_rxd_to_file.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/track_tb_iostream.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/dma_log_to_file.v
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/aes128_log_to_file.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_clkreset.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_uart_capture.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/axi_stream_io_8_txd_from_file.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ft1248x1_to_axi_streamio_v1_0.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/axi_stream_io_8_rxd_to_file.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/track_tb_iostream.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ft1248x1_track.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/dma_log_to_file.v
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/aes128_log_to_file.v
\ No newline at end of file

flist/test_io/usrt_ip.flist

@@ -16,4 +16,4 @@
 +libext+.v+.vlib
 
 // =============   APB USRT search path    =============
-$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_apb_usrt.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_apb_usrt.v
\ No newline at end of file

generic-lib @ f5886f46

-Subproject commit 1c51bdc9f94ff66bc8434aa97c397bc9c06d14ab
+Subproject commit f5886f46ad61255996214720ab13e0b006530699

nanosoc @ ab2f30d5

-Subproject commit 743692b2f1e8b803290cf60f379681db3e6c9517
+Subproject commit ab2f30d5531ee4ea52b932317b5c223800c84798

set_env.sh

@@ -61,15 +61,6 @@ if [ ! -f $PROJECT_DIR/.socinit ]; then
     echo "Running First Time Repository Initialisation"
     # Source environment variables for all submodules
     cd $DESIGN_ROOT
-    for d in $PROJECT_DIR/* ; do
-        if [ -e "$d/.git" ]; then
-            if [ -f "$d/set_env.sh" ]; then
-            # If .git file exists - submodule
-                # git config -f .gitmodules submodule.$d.branch main
-                git submodule set-branch --branch main $d
-            fi
-        fi
-    done
     git submodule update --remote --recursive
     git submodule foreach --recursive git checkout main
     # Read proj-branch file to find out which branch each subrepo needs to be on

simulate/socsim/system_secworks_sha256.sh

@@ -11,10 +11,6 @@
 
 #!/usr/bin/env bash
 
-# Generate Stimulus from stimulus generation Script
-# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
-# Create Simulatiom Directory to Run in
-
 # Get simulation name from name of script
 SIM_NAME=`basename -s .sh "$0"`
 
@@ -23,9 +19,13 @@ SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
 
 # Create Directory to put simulation files
 mkdir -p $SIM_DIR
-
 cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
+
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
-make -C $NANOSOC_TECH_DIR/systems/mcu/rtl_sim compile_xm \
-    SIM_DIR=$SIM_DIR
+echo ${2}
+make -C $NANOSOC_TECH_DIR/systems/mcu run_xm \
+    SIM_DIR=$SIM_DIR \
+    ADP_FILE=$PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
+    ${@:2}
+