SOC1-167: Updated filelist to lead to successful simulaiton compilation and...

SOC1-167: Updated filelist to lead to successful simulaiton compilation and added system simulation socsim script

env/dependency_env.sh

@@ -23,6 +23,12 @@ export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator-wrapper"
 # NanoSoC
 export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc"
 
+# FPGA Libraries
+export FPGA_LIB_TECH_DIR="$PROJECT_DIR/fpga-lib"
+
+# Generic Libraries
+export GENERIC_LIB_TECH_DIR="$PROJECT_DIR/generic-lib"
+
 #-----------------------------------------------------------------------------
 # Flows
 #-----------------------------------------------------------------------------

flist/generic_lib/generic_lib_ip.flist

@@ -16,10 +16,10 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
-$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDIO.v
-$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSSIO.v
-$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDSOC.v
-$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSS.v
-$(NANOSOC_TECH_DIR)/GLIB/mem/verilog/SROM_Ax32.v
-$(NANOSOC_TECH_DIR)/GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
+$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
+$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
+$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
+$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
+$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
+$(GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
+$(GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file

flist/nanosoc/nanosoc_chip_ip.flist

@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip_pads.v
 
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_cpu.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sysio.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
 
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
 
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/bootrom.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ahb_bootrom.v
\ No newline at end of file

flist/nanosoc/nanosoc_matrix_ip.flist

@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
++incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
 
--y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
+-y $(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    DMA-230 search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/
++incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/
 
 // - Top-level testbench
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/tb_nanosoc.v
 
 // - Testbench components
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_txd_from_file.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_rxd_to_file.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/track_tb_iostream.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/dma_log_to_file.v
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/aes128_log_to_file.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_clkreset.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_uart_capture.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_txd_from_file.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_rxd_to_file.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/track_tb_iostream.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_track.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/dma_log_to_file.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/aes128_log_to_file.v
\ No newline at end of file

flist/nanosoc/nanosoc_test_io_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Chip Test Interface IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC Chip Test Interface IP Filelists   =============
+-f $(PROJECT_DIR)/flist/test_io/adp-control_ip.flist
+-f $(PROJECT_DIR)/flist/test_io/ft1248_ip.flist
+-f $(PROJECT_DIR)/flist/test_io/usrt_ip.flist
\ No newline at end of file

flist/project/system.flist

@@ -36,6 +36,9 @@
 // - NanoSoC Bus Matrix
 -f $(PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
 
+// - NanoSoc Test Interface IP
+-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
+
 // - Generic Pad Library
 -f $(PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
 
@@ -48,11 +51,6 @@
 // - DMA controller
 -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
 
-// - Debug Controllers
--f $(PROJECT_DIR)/flist/debug/usrt_ip.flist
--f $(PROJECT_DIR)/flist/debug/adp-control_ip.flist
--f $(PROJECT_DIR)/flist/debug/ft1248_vip.flist
-
 // - Cortex-M0 IP
 -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
 

flist/debug/adp-control_ip.flist → flist/test_io/adp-control_ip.flist

@@ -16,5 +16,5 @@
 +libext+.v+.vlib
 
 // =============    ADP Control search path    =============
-$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
-$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPmanager.v
+$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPcontrol_v1_0.v
+$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPmanager.v
\ No newline at end of file

flist/debug/ft1248_vip.flist → flist/test_io/ft1248_ip.flist

@@ -16,4 +16,4 @@
 +libext+.v+.vlib
 
 // =============    FT1248 VIP search path    =============
-$(NANOSOC_TECH_DIR)/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+$(NANOSOC_TECH_DIR)/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
\ No newline at end of file

flist/debug/usrt_ip.flist → flist/test_io/usrt_ip.flist

@@ -16,4 +16,4 @@
 +libext+.v+.vlib
 
 // =============   APB USRT search path    =============
-$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v
+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_apb_usrt.v
\ No newline at end of file

nanosoc @ 743692b2

-Subproject commit c08808a5981fe0e402cc7b47b0fae6b559f18e75
+Subproject commit 743692b2f1e8b803290cf60f379681db3e6c9517

simulate/socsim/system_secworks_sha256.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Generate Stimulus from stimulus generation Script
+# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
+# Create Simulatiom Directory to Run in
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+
+cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+make -C $NANOSOC_TECH_DIR/systems/mcu/rtl_sim compile_xm \
+    SIM_DIR=$SIM_DIR

simulate/socsim/wrapper_secworks_sha256.sh

 #-----------------------------------------------------------------------------
-# SoC Labs icarus verilog simulation script for engine testbench
+# SoC Labs Simulation script for wrapper level verification testbench
 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 #
 # Contributors

socsim @ 78e5c225

-Subproject commit 550534f90e957c4ecc652e9cdd6372869c9a21a2
+Subproject commit 78e5c225440a1dbac511d22f1dec39fa51702e6d