diff --git a/env/dependency_env.sh b/env/dependency_env.sh index 39edeb95950738ff4b1ed9be6592d465f396927a..c35c74c341ae0d9c87a2d649af25781ea5ea6040 100755 --- a/env/dependency_env.sh +++ b/env/dependency_env.sh @@ -23,6 +23,12 @@ export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator-wrapper" # NanoSoC export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc" +# FPGA Libraries +export FPGA_LIB_TECH_DIR="$PROJECT_DIR/fpga-lib" + +# Generic Libraries +export GENERIC_LIB_TECH_DIR="$PROJECT_DIR/generic-lib" + #----------------------------------------------------------------------------- # Flows #----------------------------------------------------------------------------- diff --git a/flist/generic_lib/generic_lib_ip.flist b/flist/generic_lib/generic_lib_ip.flist index dd57578327c934224b000baa3688e1ce2dfba346..0ff3038bcb4fffc91f9215421f0c168dd5908e43 100644 --- a/flist/generic_lib/generic_lib_ip.flist +++ b/flist/generic_lib/generic_lib_ip.flist @@ -16,10 +16,10 @@ +libext+.v+.vlib // ============= Accelerator Module search path ============= -$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v -$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDIO.v -$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSSIO.v -$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VDDSOC.v -$(NANOSOC_TECH_DIR)/GLIB/pads/verilog/PAD_VSS.v -$(NANOSOC_TECH_DIR)/GLIB/mem/verilog/SROM_Ax32.v -$(NANOSOC_TECH_DIR)/GLIB/sync/verilog/SYNCHRONIZER_EDGES.v \ No newline at end of file +$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v +$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v +$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v +$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v +$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v +$(GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v +$(GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist index 3d40778e6b7397d557e549bdcf434529609906d8..f45acfcbdd5b8ee946abdcc31c9169de967f15b5 100644 --- a/flist/nanosoc/nanosoc_chip_ip.flist +++ b/flist/nanosoc/nanosoc_chip_ip.flist @@ -16,18 +16,18 @@ +libext+.v+.vlib // ============= NanoSoC Bus Matrix IP search path ============= -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_chip_pads.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_cpu.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sysio.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/nanosoc_sys_ahb_decode.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_pin_mux.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_clkctrl.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_mcu_sysctrl.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v \ No newline at end of file +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/bootrom.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ahb_bootrom.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_matrix_ip.flist b/flist/nanosoc/nanosoc_matrix_ip.flist index d8883e00ca6d36ba480fa5894f70af5781dcceae..409d0b4f84afcb6b701e34defcb3f4b23925dc14 100644 --- a/flist/nanosoc/nanosoc_matrix_ip.flist +++ b/flist/nanosoc/nanosoc_matrix_ip.flist @@ -16,6 +16,6 @@ +libext+.v+.vlib // ============= NanoSoC Bus Matrix IP search path ============= -+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix ++incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix --y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix \ No newline at end of file +-y $(NANOSOC_TECH_DIR)/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist index 22c13103bbf6eba70ea80d734890288613678bac..98c2d83b61c3ee6005c197b65d0918e31e89d0b9 100644 --- a/flist/nanosoc/nanosoc_tb.flist +++ b/flist/nanosoc/nanosoc_tb.flist @@ -16,18 +16,18 @@ +libext+.v+.vlib // ============= DMA-230 search path ============= -+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ ++incdir+$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ // - Top-level testbench -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/tb_nanosoc.v // - Testbench components -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_txd_from_file.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_rxd_to_file.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/track_tb_iostream.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_track.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/dma_log_to_file.v -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/aes128_log_to_file.v \ No newline at end of file +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_clkreset.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_uart_capture.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_txd_from_file.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/axi_streamio8_rxd_to_file.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/track_tb_iostream.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/ft1248x1_track.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/dma_log_to_file.v +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/aes128_log_to_file.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_test_io_ip.flist b/flist/nanosoc/nanosoc_test_io_ip.flist new file mode 100644 index 0000000000000000000000000000000000000000..022601c934131cd682ad4d215c1a1c76fd0f5532 --- /dev/null +++ b/flist/nanosoc/nanosoc_test_io_ip.flist @@ -0,0 +1,21 @@ +//----------------------------------------------------------------------------- +// NanoSoC Chip Test Interface IP Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Chip Test Interface IP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Chip Test Interface IP Filelists ============= +-f $(PROJECT_DIR)/flist/test_io/adp-control_ip.flist +-f $(PROJECT_DIR)/flist/test_io/ft1248_ip.flist +-f $(PROJECT_DIR)/flist/test_io/usrt_ip.flist \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index e4871a5cc8a699880437093dbd3370acb700e6ca..2b2b0f148cea235344edc2c7bad5e344db901b3a 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -36,6 +36,9 @@ // - NanoSoC Bus Matrix -f $(PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist +// - NanoSoc Test Interface IP +-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist + // - Generic Pad Library -f $(PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist @@ -48,11 +51,6 @@ // - DMA controller -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist -// - Debug Controllers --f $(PROJECT_DIR)/flist/debug/usrt_ip.flist --f $(PROJECT_DIR)/flist/debug/adp-control_ip.flist --f $(PROJECT_DIR)/flist/debug/ft1248_vip.flist - // - Cortex-M0 IP -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist diff --git a/flist/debug/adp-control_ip.flist b/flist/test_io/adp-control_ip.flist similarity index 85% rename from flist/debug/adp-control_ip.flist rename to flist/test_io/adp-control_ip.flist index 89ef0afee88e7561768f91b14b3da1356b8742dc..2173341ea7a7717ff62699c797cb6867a83e2757 100644 --- a/flist/debug/adp-control_ip.flist +++ b/flist/test_io/adp-control_ip.flist @@ -16,5 +16,5 @@ +libext+.v+.vlib // ============= ADP Control search path ============= -$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v -$(NANOSOC_TECH_DIR)/IPLIB/ADPcontrol_v1_0/ADPmanager.v \ No newline at end of file +$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPcontrol_v1_0.v +$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPmanager.v \ No newline at end of file diff --git a/flist/debug/ft1248_vip.flist b/flist/test_io/ft1248_ip.flist similarity index 90% rename from flist/debug/ft1248_vip.flist rename to flist/test_io/ft1248_ip.flist index 870fbbf03611b7071261422520d5597a0b1fa7c9..f7442aa7bb0351119cd97e2146b9a1b5643a4ac3 100644 --- a/flist/debug/ft1248_vip.flist +++ b/flist/test_io/ft1248_ip.flist @@ -16,4 +16,4 @@ +libext+.v+.vlib // ============= FT1248 VIP search path ============= -$(NANOSOC_TECH_DIR)/IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v \ No newline at end of file +$(NANOSOC_TECH_DIR)/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v \ No newline at end of file diff --git a/flist/debug/usrt_ip.flist b/flist/test_io/usrt_ip.flist similarity index 91% rename from flist/debug/usrt_ip.flist rename to flist/test_io/usrt_ip.flist index d2e8c5d5fc8606b9d8b456d97b615594bd81cf4e..3f8b0bb71618262cf832d825683402c1ab508117 100644 --- a/flist/debug/usrt_ip.flist +++ b/flist/test_io/usrt_ip.flist @@ -16,4 +16,4 @@ +libext+.v+.vlib // ============= APB USRT search path ============= -$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_apb_usrt.v \ No newline at end of file +$(NANOSOC_TECH_DIR)/systems/mcu/verilog/cmsdk_apb_usrt.v \ No newline at end of file diff --git a/nanosoc b/nanosoc index c08808a5981fe0e402cc7b47b0fae6b559f18e75..743692b2f1e8b803290cf60f379681db3e6c9517 160000 --- a/nanosoc +++ b/nanosoc @@ -1 +1 @@ -Subproject commit c08808a5981fe0e402cc7b47b0fae6b559f18e75 +Subproject commit 743692b2f1e8b803290cf60f379681db3e6c9517 diff --git a/simulate/socsim/system_secworks_sha256.sh b/simulate/socsim/system_secworks_sha256.sh new file mode 100755 index 0000000000000000000000000000000000000000..8d282fbc2625d3cbdf3e15959b49f7388ef2cce3 --- /dev/null +++ b/simulate/socsim/system_secworks_sha256.sh @@ -0,0 +1,31 @@ +#----------------------------------------------------------------------------- +# SoC Labs Simulation script for system level verification +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright 2023, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +#!/usr/bin/env bash + +# Generate Stimulus from stimulus generation Script +# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py +# Create Simulatiom Directory to Run in + +# Get simulation name from name of script +SIM_NAME=`basename -s .sh "$0"` + +# Directory to put simulation files +SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME + +# Create Directory to put simulation files +mkdir -p $SIM_DIR + +cd $PROJECT_DIR/simulate/sim/system_secworks_sha256 +# Compile Simulation +# Call makefile in NanoSoC Repo with options +make -C $NANOSOC_TECH_DIR/systems/mcu/rtl_sim compile_xm \ + SIM_DIR=$SIM_DIR diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh index 4f7780aebcf3b542b6bcb7386fbee47bddc12939..0007d9cd9b3feb343f13810f63ed67941e324620 100755 --- a/simulate/socsim/wrapper_secworks_sha256.sh +++ b/simulate/socsim/wrapper_secworks_sha256.sh @@ -1,5 +1,5 @@ #----------------------------------------------------------------------------- -# SoC Labs icarus verilog simulation script for engine testbench +# SoC Labs Simulation script for wrapper level verification testbench # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. # # Contributors diff --git a/socsim b/socsim index 550534f90e957c4ecc652e9cdd6372869c9a21a2..78e5c225440a1dbac511d22f1dec39fa51702e6d 160000 --- a/socsim +++ b/socsim @@ -1 +1 @@ -Subproject commit 550534f90e957c4ecc652e9cdd6372869c9a21a2 +Subproject commit 78e5c225440a1dbac511d22f1dec39fa51702e6d