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Commit 09e374da authored by David Mapstone's avatar David Mapstone
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SOC1-159: Started to generate registers for wrapper

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.gitmodules
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......@@ -10,3 +10,6 @@
[submodule "socsim"]
path = socsim
url = git@git.soton.ac.uk:soclabs/socsim.git
[submodule "CHIPKIT"]
path = CHIPKIT
url = git@git.soton.ac.uk:soclabs/CHIPKIT.git
CHIPKIT @ 2435cd9d
Subproject commit 2435cd9df8ff8a7e7d2e289b4e646eed10882e27
set_env.sh
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......@@ -36,7 +36,7 @@ else
# Source environment variables for all submodules
for d in $SOC_TOP_DIR/* ; do
if [ -f "$d/.git" ]; then
if [ -e "$d/.git" ]; then
if [ -f "$d/set_env.sh" ]; then
# If .git file exists - submodule
source $d/set_env.sh
......
sha-2-accelerator @ bbd478b9
Compare 1dd9a82c...bbd478b9
Subproject commit 1dd9a82ce6170d363933240053894e8f84928e55
Subproject commit bbd478b94f719df99ade719c546cfad52dd24e40
wrapper/regs/cregs.csv 0 → 100644
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name idx nbits start access test rval desc
# Wrapper Control Register
accelerator_en 0 32 0 rw 0 0x00000000 Accelerator Enable Register
accelerator_channel_en 1 32 0 rw 0 0x00000000 Accelerator Channel Enable Register
\ No newline at end of file
wrapper/regs/cregs/CREGS.h 0 → 100644
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
#ifndef CREGS_H
#define CREGS_H
typedef struct
{
__IO uint32_t ACCELERATOR_EN; /* Offset: 0x0 (R/W) Accelerator Enable Register */
__IO uint32_t ACCELERATOR_CHANNEL_EN; /* Offset: 0x4 (R/W) Accelerator Channel Enable Register */
} CREGS_TypeDef;
#endif
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/regs/cregs/cregs.inst.sv 0 → 100644
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
// START
logic [31:0] accelerator_en;
logic [31:0] accelerator_channel_en;
cregs u_cregs (
// clocks and resets
.clk(pclk),
.rstn(presetn),
// Synchronous register interface
.regbus (cregs.sink),
// reg file signals
.accelerator_en(accelerator_en[31:0]) /* idx 0 */,
.accelerator_channel_en(accelerator_channel_en[31:0]) /* idx 1 */
);
// END
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/regs/cregs/cregs.md 0 → 100644
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
# Programmers Model
## Module: CREGS
| Address Offset | Signal Name | Access | Bit width | Start bit | Description |
| --- | --- | --- | --- | --- | --- |
|
| 0x0 | **ACCELERATOR_EN** | RW | 32 | 0 | Accelerator Enable Register |
| 0x4 | **ACCELERATOR_CHANNEL_EN** | RW | 32 | 0 | Accelerator Channel Enable Register |
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/regs/cregs/cregs.py 0 → 100644
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# // VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
class Cregs(object):
def __init__(self,base_offset):
self.base_offset = base_offset
self.ACCELERATOR_EN = self.base_offset + 0x0 # Accelerator Enable Register
self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
# // VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
//-----------------------------------------------------------------------------
// SoC Labs APB register Template
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
// VGEN: HEADER
// Register file contents:
//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
// VGEN: MODULE NAME
module cregs (
// clocks and resets
input logic clk,
input logic rstn,
// APB inteface
input logic psel,
input logic [ADDRWIDTH:0] paddr,
input logic penable,
input logic pwrite,
input logic [31:0] pwdata,
output logic [31:0] prdata,
output logic pready,
output logic pslverr,
// VGEN: INPUTS TO REGS
// VGEN: OUTPUTS FROM REGS
output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
);
//------------------------------------------------------------------------------
// APB Interface
//------------------------------------------------------------------------------
logic [ADDRWIDTH-1:0] addr;
logic read_en;
logic write_en;
logic [31:0] wdata;
logic [31:0] rdata;
// APB interface
assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
// register read and write signal
assign addr = paddr;
assign read_en = psel & (~pwrite); // assert for whole apb read transfer
assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
// It is also possible to change the design to perform the write in the 2nd
// APB cycle. E.g.
// assign write_en = psel & penable & pwrite;
// However, if the design generate waitstate, this expression will result
// in write_en being asserted for multiple cycles.
assign wdata = pwdata;
assign prdata = rdata;
//------------------------------------------------------------------------------
// Regsiter write
//------------------------------------------------------------------------------
// VGEN: REG WRITE
// idx #0
logic [31:0] accelerator_en_reg;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
accelerator_en_reg[31:0] <= '0;
end else begin
if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
end
end
assign accelerator_en[31:0] = accelerator_en_reg[31:0];
// idx #1
logic [31:0] accelerator_channel_en_reg;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
accelerator_channel_en_reg[31:0] <= '0;
end else begin
if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
end
end
assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
//------------------------------------------------------------------------------
// Regsiter read
//------------------------------------------------------------------------------
logic [31:0] rdata_o;
always @*
begin
if (read_en)
begin
rdata_o[31:0] = 32'h00000000;
// VGEN: REG READ
if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
end
else
begin
rdata_o[31:0] = {32'h00000000};
end
end
assign rdata[31:0] = rdata_o[31:0];
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
endmodule
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/regs/cregs/cregs.sv.bak 0 → 100644
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
//-----------------------------------------------------------------------------
// SoC Labs APB register Template
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
// VGEN: HEADER
// Register file contents:
//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
// VGEN: MODULE NAME
module cregs (
// clocks and resets
input logic clk,
input logic rstn,
// APB inteface
input logic psel,
input logic [ADDRWIDTH:0] paddr,
input logic penable,
input logic pwrite,
input logic [31:0] pwdata,
output logic [31:0] prdata,
output logic pready,
output logic pslverr,
// VGEN: INPUTS TO REGS
// VGEN: OUTPUTS FROM REGS
output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
);
//------------------------------------------------------------------------------
// APB Interface
//------------------------------------------------------------------------------
logic [ADDRWIDTH-1:0] addr;
logic read_en;
logic write_en;
logic [31:0] wdata;
logic [31:0] rdata;
// APB interface
assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
// register read and write signal
assign addr = paddr;
assign read_en = psel & (~pwrite); // assert for whole apb read transfer
assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
// It is also possible to change the design to perform the write in the 2nd
// APB cycle. E.g.
// assign write_en = psel & penable & pwrite;
// However, if the design generate waitstate, this expression will result
// in write_en being asserted for multiple cycles.
assign wdata = pwdata;
assign prdata = rdata;
//------------------------------------------------------------------------------
// Regsiter write
//------------------------------------------------------------------------------
// VGEN: REG WRITE
// idx #0
logic [31:0] accelerator_en_reg;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
accelerator_en_reg[31:0] <= '0;
end else begin
if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
end
end
assign accelerator_en[31:0] = accelerator_en_reg[31:0];
// idx #1
logic [31:0] accelerator_channel_en_reg;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
accelerator_channel_en_reg[31:0] <= '0;
end else begin
if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
end
end
assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
//------------------------------------------------------------------------------
// Regsiter read
//------------------------------------------------------------------------------
logic [31:0] rdata_o;
always @*
begin
if (read_en)
begin
rdata_o[31:0] = 32'h00000000;
// VGEN: REG READ
if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
end
else
begin
rdata_o[31:0] = {32'h00000000};
end
end
assign rdata[31:0] = rdata_o[31:0];
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
endmodule
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
wrapper/regs/cregs/cregs_test.c 0 → 100644
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// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
#include "cregs_test.h"
// This test is intended to check initial (reset) values of registers
int cregs_initial_value_test(void) {
int num_errors=0;
if (SM2_CREGS->ACCELERATOR_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");}
if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");}
return num_errors;
}
// This test is intended to check write read to registers
int cregs_write_read_test(void) {
int num_errors=0;
SM2_CREGS->ACCELERATOR_EN = 0xFFFFFFFF; // write all-1s
if (SM2_CREGS->ACCELERATOR_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-1s
SM2_CREGS->ACCELERATOR_EN = 0x0; // clear field
if (SM2_CREGS->ACCELERATOR_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-0s
SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0xFFFFFFFF; // write all-1s
if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-1s
SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0x0; // clear field
if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-0s
return num_errors;
}
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/regs/cregs/cregs_test.h 0 → 100644
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− 0
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// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
#ifndef CREGS_TEST_H
#define CREGS_TEST_H
#include "SM2_CM0.h"
// This test is intended to check initial (reset) values of registers
int cregs_initial_value_test(void);
// This test is intended to check write and read to registers
int cregs_write_read_test(void);
#endif
// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
wrapper/src/wrapper_sha256_hashing_stream.sv
+ 76
− 42
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......@@ -10,7 +10,7 @@
//-----------------------------------------------------------------------------
module wrapper_sha256_hashing_stream #(
parameter ADDRWIDTH=12,
parameter AHBADDRWIDTH=12,
parameter INPACKETWIDTH=512,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
......@@ -19,18 +19,20 @@ module wrapper_sha256_hashing_stream #(
input logic HCLK, // Clock
input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
input logic [ADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
// AHB connection to Initiator
input logic HSELS,
input logic [AHBADDRWIDTH-1:0] HADDRS,
input logic [1:0] HTRANSS,
input logic [2:0] HSIZES,
input logic HWRITES,
input logic HREADYS,
input logic [31:0] HWDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS,
output logic HREADYOUTS,
output logic HRESPS,
output logic [31:0] HRDATAS,
//TODO: Add APB Interface
// Input Data Request Signal to DMAC
output logic in_data_req,
......@@ -39,20 +41,25 @@ module wrapper_sha256_hashing_stream #(
output logic out_data_req
);
//----------------------------------------------------------
// Internal Parameters
//----------------------------------------------------------
//**********************************************************
// Internal AHB Parameters
//**********************************************************
// Input Port Parameters
localparam [ADDRWIDTH-1:0] INPORTADDR = 'h000;
localparam INPORTADDRWIDTH = ADDRWIDTH - 1;
localparam [AHBADDRWIDTH-1:0] INPORTADDR = 'h000;
localparam INPORTAHBADDRWIDTH = AHBADDRWIDTH - 1;
// Output Port Parameters
localparam [ADDRWIDTH-1:0] OUTPORTADDR = 'h800;
localparam OUTPORTADDRWIDTH = ADDRWIDTH - 1;
localparam [AHBADDRWIDTH-1:0] OUTPORTADDR = 'h800;
localparam OUTPORTAHBADDRWIDTH = AHBADDRWIDTH - 1;
localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
localparam OUTPACKETSPACEWIDTH = OUTPORTADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
//**********************************************************
// Wrapper AHB Components
//**********************************************************
//----------------------------------------------------------
// Internal AHB Decode Logic
......@@ -155,7 +162,7 @@ module wrapper_sha256_hashing_stream #(
// Packet Constructor Instantiation
wrapper_ahb_packet_constructor #(
ADDRWIDTH-1,
INPORTAHBADDRWIDTH,
INPACKETWIDTH
) u_wrapper_data_input_port (
.hclk (HCLK),
......@@ -163,7 +170,7 @@ module wrapper_sha256_hashing_stream #(
// Input slave port: 32 bit data bus interface
.hsels (hsel0),
.haddrs (HADDRS[ADDRWIDTH-2:0]),
.haddrs (HADDRS[AHBADDRWIDTH-2:0]),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
......@@ -213,14 +220,14 @@ module wrapper_sha256_hashing_stream #(
logic out_packet_ready;
// Relative Read Address for Start of Current Block
logic [OUTPORTADDRWIDTH-1:0] block_read_addr;
logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr;
// Block Packets Remaining Tie-off (only ever one packet per block)
assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}};
// Packet Deconstructor Instantiation
wrapper_ahb_packet_deconstructor #(
ADDRWIDTH-1,
OUTPORTAHBADDRWIDTH,
OUTPACKETWIDTH
) u_wrapper_data_output_port (
.hclk (HCLK),
......@@ -228,7 +235,7 @@ module wrapper_sha256_hashing_stream #(
// Input slave port: 32 bit data bus interface
.hsels (hsel1),
.haddrs (HADDRS[ADDRWIDTH-2:0]),
.haddrs (HADDRS[AHBADDRWIDTH-2:0]),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
......@@ -253,6 +260,50 @@ module wrapper_sha256_hashing_stream #(
.block_read_addr (block_read_addr)
);
//----------------------------------------------------------
// Default AHB Target Logic
//----------------------------------------------------------
// AHB Default Target Instantiation
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel2),
.HTRANS (HTRANSS),
.HREADY (HREADYS),
.HREADYOUT (hreadyout2),
.HRESP (hresp2)
);
// Default Targets Data is tied off
assign hrdata2 = {32{1'b0}};
//**********************************************************
// Wrapper APB Components
//**********************************************************
// TODO: Instantiate APB Mux
// TODO: Instantiate APB Default Target
// TODO: Wrapper Register Blocks
//**********************************************************
// Wrapper Interrupt Generation
//**********************************************************
// TODO: Instantiate IRQ Generator
//**********************************************************
// Wrapper DMA Data Request Generation
//**********************************************************
// TODO: Write up data request logic through registers
//**********************************************************
// Accelerator Engine
//**********************************************************
//----------------------------------------------------------
// Accelerator Engine Logic
//----------------------------------------------------------
......@@ -284,22 +335,5 @@ module wrapper_sha256_hashing_stream #(
.data_out_ready (out_packet_ready)
);
//----------------------------------------------------------
// Default AHB Target Logic
//----------------------------------------------------------
// AHB Default Target Instantiation
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (hsel2),
.HTRANS (HTRANSS),
.HREADY (HREADYS),
.HREADYOUT (hreadyout2),
.HRESP (hresp2)
);
// Default Targets Data is tied off
assign hrdata2 = {32{1'b0}};
endmodule
\ No newline at end of file
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