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Commit 8f88e7b4 authored by David Mapstone's avatar David Mapstone
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SOC1-122: Moved system files from nanosoc repo to top-level

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//-----------------------------------------------------------------------------
// Accelerator System Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Top-level Accelerator System
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(SOC_TOP_DIR)/system/src/
+incdir+$(SOC_TOP_DIR)/system/src/
$(SOC_TOP_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file
#-----------------------------------------------------------------------------
# ADP Command File Verification Script
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright � 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
class address_region():
def __init__(self, base, size):
self.base = base
self.size = size
self.end = base + size - 4
class read_word():
def __init__(self, index, region, address, read_data = 0,exp_data = 0):
self.index = index
self.region = region
self.address = int(str(address), 16)
self.read_data = int(str(read_data), 16)
self.exp_data = int(str(exp_data), 16)
def validate(self):
if (self.address >= self.region.base and self.address <= self.region.end):
return True
else:
return False
def check_address(self, address):
# print(f"self: {hex(self.address)} test: {address}")
if (self.address == int(str(address), 16)):
return True
else:
return False
def set_read_data(self, read_data):
self.read_data = int(read_data, 16)
def set_exp_data(self, exp_data):
self.exp_data = int(exp_data, 16)
def verify(self):
assert (self.read_data == self.exp_data)
def adp_verify(adp_input, adp_output, out_log):
# Create Input Region for Accelerator
accel_input_port = address_region(base = 0x6001_0000, size = 0x0000_0800)
accel_output_port = address_region(base = 0x6001_0800, size = 0x0000_0800)
word_list = []
temp_address_buf = 0x0
# Read in adp input
adp_input_lines = open(adp_input, "r").readlines()
idx = 0
for line in adp_input_lines:
line_split = str(line).split()
if len(line_split) > 1:
if line_split[0].lower() == "a":
# Capture Address
temp_address_buf = line_split[1]
if line_split[0].lower() == "r":
temp_read_word = read_word(idx, accel_output_port, temp_address_buf, exp_data = line_split[1])
if temp_read_word.validate():
word_list.append(temp_read_word)
idx += 1
# Read in adp output
adp_output_lines = open(adp_output, "r").readlines()
idx = 0
temp_address_buf = 0x0
for line in adp_output_lines:
line_split = str(line).split()
if len(line_split) > 1:
if line_split[0] == "]A":
# Capture Address
temp_address_buf = line_split[1]
if line_split[0] == "]R":
if word_list[idx].check_address(temp_address_buf):
word_list[idx].set_read_data(line_split[1])
idx += 1
# Perform Verification
for word in word_list:
word.verify()
print(f"Tests Passed on {len(word_list)} reads")
if __name__ == "__main__":
adp_input = "ft1248_ip.log"
adp_output = "ft1248_op.log"
output_log = "verify.log"
adp_verify(adp_input,adp_output,output_log)
Subproject commit 6138eb07a20f6394b39ea5f53f553a4300d8b6e4
Subproject commit 20e2a3d1520f66949bee7efad07e4b61aa3741a0
#-----------------------------------------------------------------------------
# SoC Labs Cadence Xcelium simulation script for engine testbench
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2022, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
mkdir -p $SOC_TOP_DIR/simulate/sim/
make run_xm \
TESTNAME=hello \
ACCELERATOR_VC="-sv -f $ACC_ENGINE_DIR/flist/sha-2-accelerator_src.flist -f $ACC_WRAPPER_DIR/flist/wrapper_ip.flist" \
ADP_FILE="$SOC_TOP_DIR/system/stimulus/adp_hash_stim.cmd" \
-C $NANOSOC_DIR/Cortex-M0/nanosoc/systems/mcu/rtl_sim
\ No newline at end of file
//-----------------------------------------------------------------------------
// Nanosoc Expansion Region AHB Address Region
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "cmsdk_ahb_default_slave.v"
`include "cmsdk_ahb_slave_mux.v"
module nanosoc_exp #(
parameter ADDRWIDTH=29, // Region Address Width
parameter ACCEL_ADDRWIDTH=12 // Region Address Width
)(
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSELS,
input wire [ADDRWIDTH-1:0] HADDRS,
input wire [1:0] HTRANSS,
input wire [2:0] HSIZES,
input wire HWRITES,
input wire HREADYS,
input wire [31:0] HWDATAS,
output wire HREADYOUTS,
output wire HRESPS,
output wire [31:0] HRDATAS
);
//********************************************************************************
// Internal Wires
//********************************************************************************
// Accelerator AHB Signals
wire HSEL0;
wire HREADYOUT0;
wire HRESP0;
wire [31:0] HRDATA0;
// Default Slave AHB Signals
wire HSEL1;
wire HREADYOUT1;
wire HRESP1;
wire [31:0] HRDATA1;
//********************************************************************************
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default target
assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
assign HSEL1 = HSEL0 ? 1'b0:1'b1;
//********************************************************************************
// Slave multiplexer module:
// multiplex the target signals to master, three ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
1, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
0, //PORT6_ENABLE
0, //PORT7_ENABLE
0, //PORT8_ENABLE
0 //PORT9_ENABLE
) u_ahb_slave_mux (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADYS),
.HSEL0 (HSEL0), // Input Port 0
.HREADYOUT0 (HREADYOUT0),
.HRESP0 (HRESP0),
.HRDATA0 (HRDATA0),
.HSEL1 (HSEL1), // Input Port 1
.HREADYOUT1 (HREADYOUT1),
.HRESP1 (HRESP1),
.HRDATA1 (HRDATA1),
.HSEL2 (1'b0), // Input Port 2
.HREADYOUT2 (),
.HRESP2 (),
.HRDATA2 (),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
.HRDATA3 (),
.HSEL4 (1'b0), // Input Port 4
.HREADYOUT4 (),
.HRESP4 (),
.HRDATA4 (),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (),
.HRESP5 (),
.HRDATA5 (),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (),
.HRESP6 (),
.HRDATA6 (),
.HSEL7 (1'b0), // Input Port 7
.HREADYOUT7 (),
.HRESP7 (),
.HRDATA7 (),
.HSEL8 (1'b0), // Input Port 8
.HREADYOUT8 (),
.HRESP8 (),
.HRDATA8 (),
.HSEL9 (1'b0), // Input Port 9
.HREADYOUT9 (),
.HRESP9 (),
.HRDATA9 (),
.HREADYOUT (HREADYOUTS), // Outputs
.HRESP (HRESPS),
.HRDATA (HRDATAS)
);
//********************************************************************************
// Slave module 1: Accelerator AHB target module
//********************************************************************************
wrapper_sha256_hashing_stream #(ACCEL_ADDRWIDTH
) accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input target port: 32 bit data bus interface
.HSELS (HSEL0),
.HADDRS (HADDRS[ACCEL_ADDRWIDTH-1:0]),
.HTRANSS (HTRANSS),
.HSIZES (HSIZES),
.HWRITES (HWRITES),
.HREADYS (HREADYS),
.HWDATAS (HWDATAS),
.HREADYOUTS (HREADYOUT0),
.HRESPS (HRESP0),
.HRDATAS (HRDATA0)
);
//********************************************************************************
// Slave module 2: AHB default target module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL1),
.HTRANS (HTRANSS),
.HREADY (HREADYS),
.HREADYOUT (HREADYOUT1),
.HRESP (HRESPS)
);
assign HRDATA1 = {32{1'b0}}; // Default target don't have data
endmodule
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