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Verified Commit 3b74a1d4 authored by Minyong Li's avatar Minyong Li 💬
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core.Round: add a grouped round block

Architectural change: the flattened columnar round and diagonal
round are now stacked and controlled by a signal, which means only
one can be activated now.
parent 79ae3d38
// SPDX-FileCopyrightText: 2021 Minyong Li <>
// SPDX-License-Identifier: CERN-OHL-W-2.0
import chisel3._
class Round(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
val roundSelect = IO(Input(Bool()))
val in = IO(Input(UInt(512.W)))
val out = IO(Output(UInt(512.W)))
private val columnarRound = Module(new ColumnarRound)
private val diagonalRound = Module(new DiagonalRound) := in := in
out := Mux(roundSelect, columnarRound.out, diagonalRound.out)
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