From 3b74a1d40f68c0ac02a24fe8efcf2c08ae4a091c Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Thu, 8 Jul 2021 14:01:07 +0100
Subject: [PATCH] core.Round: add a grouped round block
Architectural change: the flattened columnar round and diagonal
round are now stacked and controlled by a signal, which means only
one can be activated now.
---
.../uk/ac/soton/ecs/can/core/Round.scala | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 src/main/scala/uk/ac/soton/ecs/can/core/Round.scala
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/Round.scala b/src/main/scala/uk/ac/soton/ecs/can/core/Round.scala
new file mode 100644
index 0000000..3477247
--- /dev/null
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/Round.scala
@@ -0,0 +1,20 @@
+// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
+// SPDX-License-Identifier: CERN-OHL-W-2.0
+
+package uk.ac.soton.ecs.can.core
+
+import chisel3._
+import uk.ac.soton.ecs.can.config.CanCoreConfiguration
+
+class Round(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
+ val roundSelect = IO(Input(Bool()))
+ val in = IO(Input(UInt(512.W)))
+ val out = IO(Output(UInt(512.W)))
+
+ private val columnarRound = Module(new ColumnarRound)
+ private val diagonalRound = Module(new DiagonalRound)
+
+ columnarRound.in := in
+ diagonalRound.in := in
+ out := Mux(roundSelect, columnarRound.out, diagonalRound.out)
+}
--
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