removed datavalid

behavioural/ahb_out.sv

@@ -47,8 +47,6 @@ module ahb_out(
 
   //Non-AHB Signals
   output logic [8:0] x1, x2, y1, y2,
-  output logic DataValid
-
 );
 
 timeunit 1ns;

behavioural/arm_soc.sv

 // Example code for an M0 AHBLite System
 //  Iain McNally
 //  ECS, University of Soutampton
-
 module arm_soc(
 
   input HCLK, HRESETn,
@@ -9,7 +8,6 @@ module arm_soc(
   input [15:0] Switches, 
   input [1:0] Buttons, 
   output logic [8:0] x1, x2, y1, y2,	
-  output DataValid,
   output LOCKUP
 
 );
@@ -94,7 +92,7 @@ timeprecision 100ps;
     .HSEL(HSEL_DOUT),
     .HRDATA(HRDATA_DOUT), .HREADYOUT(HREADYOUT_DOUT),
 
-    .x1(x1), .x2(x2), .y1(y1), .y2(y2), .DataValid(DataValid)
+    .x1(x1), .x2(x2), .y1(y1), .y2(y2)
 
   );
   

testbench/arm_soc.tcl

@@ -17,7 +17,6 @@ simvision {
     waveform  add  -signals  arm_soc_stim.x2
     waveform  add  -signals  arm_soc_stim.y1
     waveform  add  -signals  arm_soc_stim.y2    
-    waveform  add  -signals  arm_soc_stim.DataValid
     waveform  add  -signals  arm_soc_stim.LOCKUP
     waveform  add  -signals  arm_soc_stim.dut.HADDR
     waveform  add  -signals  arm_soc_stim.dut.HWRITE

testbench/arm_soc_stim.sv

@@ -7,10 +7,9 @@ timeprecision 100ps;
   logic [15:0] Switches;
   logic [1:0] Buttons;
   logic [8:0] x1,x2,y1,y2;
-  wire DataValid;
   wire LOCKUP;
 
-  arm_soc dut(.HCLK, .HRESETn, .x1, .y1, .x2, .y2, .DataValid, .Switches, .Buttons, .LOCKUP);
+  arm_soc dut(.HCLK, .HRESETn, .x1, .y1, .x2, .y2, .Switches, .Buttons, .LOCKUP);
 
   always
     begin