Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
A
ARM_SoC
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Package registry
Model registry
Operate
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
ks6n19
ARM_SoC
Commits
0eec49fb
Commit
0eec49fb
authored
4 years ago
by
ks6n19
Browse files
Options
Downloads
Patches
Plain Diff
partial addressing
parent
a863fcb6
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
behavioural/ahb_out.sv
+25
-77
25 additions, 77 deletions
behavioural/ahb_out.sv
with
25 additions
and
77 deletions
behavioural/ahb_out.sv
+
25
−
77
View file @
0eec49fb
...
@@ -59,10 +59,8 @@ timeprecision 100ps;
...
@@ -59,10 +59,8 @@ timeprecision 100ps;
//control signals are stored in registers
//control signals are stored in registers
logic
write_enable
,
read_enable
;
logic
write_enable
,
read_enable
;
logic
half_word_address_1
;
logic
[
1
:
0
]
word_address
;
logic
half_word_address_2
;
logic
half_word_address_3
;
logic
half_word_address_4
;
logic
NextDataValid
;
logic
NextDataValid
;
logic
[
15
:
0
]
Status
;
logic
[
15
:
0
]
Status
;
...
@@ -73,28 +71,21 @@ timeprecision 100ps;
...
@@ -73,28 +71,21 @@ timeprecision 100ps;
begin
begin
write_enable
<=
'0
;
write_enable
<=
'0
;
read_enable
<=
'0
;
read_enable
<=
'0
;
half_word_address_1
<=
'0
;
word_address
<=
'0
;
half_word_address_2
<=
'0
;
half_word_address_3
<=
'0
;
half_word_address_4
<=
'0
;
end
end
else
if
(
HREADY
&&
HSEL
&&
(
HTRANS
!=
No_Transfer
)
)
else
if
(
HREADY
&&
HSEL
&&
(
HTRANS
!=
No_Transfer
)
)
begin
begin
write_enable
<=
HWRITE
;
write_enable
<=
HWRITE
;
read_enable
<=
!
HWRITE
;
read_enable
<=
!
HWRITE
;
half_word_address_1
<=
HADDR
[
1
];
word_address
<=
HADDR
[
3
:
2
];
half_word_address_2
<=
HADDR
[
2
];
half_word_address_3
<=
HADDR
[
3
];
half_word_address_4
<=
HADDR
[
4
];
end
end
else
else
begin
begin
write_enable
<=
'0
;
write_enable
<=
'0
;
read_enable
<=
'0
;
read_enable
<=
'0
;
half_word_address_1
<=
'0
;
word_address
<=
'0
;
half_word_address_2
<=
'0
;
half_word_address_3
<=
'0
;
half_word_address_4
<=
'0
;
end
end
//Act on control signals in the data phase
//Act on control signals in the data phase
...
@@ -107,69 +98,24 @@ timeprecision 100ps;
...
@@ -107,69 +98,24 @@ timeprecision 100ps;
x2
<=
'0
;
x2
<=
'0
;
y1
<=
'0
;
y1
<=
'0
;
y2
<=
'0
;
y2
<=
'0
;
DataValid
<=
'0
;
NextDataValid
<=
'0
;
end
// x1 write
else
if
(
write_enable
&&
(
half_word_address_1
==
0
))
begin
x1
<=
HWDATA
[
15
:
0
];
DataValid
<=
NextDataValid
;
// this is not synthesized but provides useful debugging information
end
if
(
NextDataValid
)
// x1 write
$
display
(
"x1: "
,
HWDATA
[
15
:
0
],
" @"
,
$
time
);
else
if
(
write_enable
&&
(
word_address
==
0
))
else
x1
<=
HWDATA
[
15
:
0
];
$
display
(
"x1:--Invalid-- @"
,
$
time
);
end
// y1 write
// x2 write
else
if
(
write_enable
&&
(
word_address
==
1
))
else
if
(
write_enable
&&
(
half_word_address_2
==
0
))
y1
<=
HWDATA
[
15
:
0
];
begin
x2
<=
HWDATA
[
15
:
0
];
DataValid
<=
NextDataValid
;
// this is not synthesized but provides useful debugging information
if
(
NextDataValid
)
$
display
(
"x2: "
,
HWDATA
[
15
:
0
],
" @"
,
$
time
);
else
$
display
(
"x2:--Invalid-- @"
,
$
time
);
end
// x2 write
// y1 write
else
if
(
write_enable
&&
(
word_address
==
2
))
else
if
(
write_enable
&&
(
half_word_address_3
==
0
))
x2
<=
HWDATA
[
15
:
0
];
begin
y1
<=
HWDATA
[
15
:
0
];
DataValid
<=
NextDataValid
;
// this is not synthesized but provides useful debugging information
if
(
NextDataValid
)
$
display
(
"y1: "
,
HWDATA
[
15
:
0
],
" @"
,
$
time
);
else
$
display
(
"y1:--Invalid-- @"
,
$
time
);
end
// y2 write
//y2 write
else
if
(
write_enable
&&
(
word_address
==
3
))
else
if
(
write_enable
&&
(
half_word_address_4
==
0
))
y2
<=
HWDATA
[
15
:
0
];
begin
y2
<=
HWDATA
[
15
:
0
];
DataValid
<=
NextDataValid
;
// this is not synthesized but provides useful debugging information
if
(
NextDataValid
)
$
display
(
"y2: "
,
HWDATA
[
15
:
0
],
" @"
,
$
time
);
else
$
display
(
"y2:--Invalid-- @"
,
$
time
);
end
else
if
(
write_enable
&&
(
half_word_address_1
==
1
)
&&
(
half_word_address_2
==
1
)
&&
(
half_word_address_3
==
1
)
&&
(
half_word_address_4
==
1
)
)
begin
NextDataValid
<=
HWDATA
[
16
];
end
// define the bits in the status register
assign
Status
=
{
14'd0
,
NextDataValid
,
DataValid
}
;
//read
//read
always_comb
always_comb
...
@@ -178,10 +124,12 @@ timeprecision 100ps;
...
@@ -178,10 +124,12 @@ timeprecision 100ps;
// but may help with debugging)
// but may help with debugging)
HRDATA
=
'0
;
HRDATA
=
'0
;
else
else
case
(
half_
word_address
_1
)
case
(
word_address
)
// ensure that half-word data is correctly aligned
// ensure that half-word data is correctly aligned
0
:
HRDATA
=
{
16'd0
,
x1
}
;
0
:
HRDATA
=
{
23'd0
,
x1
}
;
1
:
HRDATA
=
{
Status
,
16'd0
}
;
1
:
HRDATA
=
{
23'd0
,
y1
}
;
2
:
HRDATA
=
{
23'd0
,
x2
}
;
3
:
HRDATA
=
{
23'd0
,
y2
}
;
// unused address - returns zero
// unused address - returns zero
default
:
HRDATA
=
'0
;
default
:
HRDATA
=
'0
;
endcase
endcase
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment