From 00fdc59a51be6e652967c8cdc7b3bbfbf614b817 Mon Sep 17 00:00:00 2001
From: ks6n19 <ks6n19@soton.ac.uk>
Date: Tue, 11 Aug 2020 12:51:52 +0100
Subject: [PATCH] removed datavalid

---
 behavioural/ahb_out.sv    | 2 --
 behavioural/arm_soc.sv    | 4 +---
 testbench/arm_soc.tcl     | 1 -
 testbench/arm_soc_stim.sv | 3 +--
 4 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/behavioural/ahb_out.sv b/behavioural/ahb_out.sv
index b455f67..42b1658 100644
--- a/behavioural/ahb_out.sv
+++ b/behavioural/ahb_out.sv
@@ -47,8 +47,6 @@ module ahb_out(
 
   //Non-AHB Signals
   output logic [8:0] x1, x2, y1, y2,
-  output logic DataValid
-
 );
 
 timeunit 1ns;
diff --git a/behavioural/arm_soc.sv b/behavioural/arm_soc.sv
index b984468..daef105 100644
--- a/behavioural/arm_soc.sv
+++ b/behavioural/arm_soc.sv
@@ -1,7 +1,6 @@
 // Example code for an M0 AHBLite System
 //  Iain McNally
 //  ECS, University of Soutampton
-
 module arm_soc(
 
   input HCLK, HRESETn,
@@ -9,7 +8,6 @@ module arm_soc(
   input [15:0] Switches, 
   input [1:0] Buttons, 
   output logic [8:0] x1, x2, y1, y2,	
-  output DataValid,
   output LOCKUP
 
 );
@@ -94,7 +92,7 @@ timeprecision 100ps;
     .HSEL(HSEL_DOUT),
     .HRDATA(HRDATA_DOUT), .HREADYOUT(HREADYOUT_DOUT),
 
-    .x1(x1), .x2(x2), .y1(y1), .y2(y2), .DataValid(DataValid)
+    .x1(x1), .x2(x2), .y1(y1), .y2(y2)
 
   );
   
diff --git a/testbench/arm_soc.tcl b/testbench/arm_soc.tcl
index eb5dfa5..dda1a4b 100644
--- a/testbench/arm_soc.tcl
+++ b/testbench/arm_soc.tcl
@@ -17,7 +17,6 @@ simvision {
     waveform  add  -signals  arm_soc_stim.x2
     waveform  add  -signals  arm_soc_stim.y1
     waveform  add  -signals  arm_soc_stim.y2    
-    waveform  add  -signals  arm_soc_stim.DataValid
     waveform  add  -signals  arm_soc_stim.LOCKUP
     waveform  add  -signals  arm_soc_stim.dut.HADDR
     waveform  add  -signals  arm_soc_stim.dut.HWRITE
diff --git a/testbench/arm_soc_stim.sv b/testbench/arm_soc_stim.sv
index 7b12257..98ebdb8 100644
--- a/testbench/arm_soc_stim.sv
+++ b/testbench/arm_soc_stim.sv
@@ -7,10 +7,9 @@ timeprecision 100ps;
   logic [15:0] Switches;
   logic [1:0] Buttons;
   logic [8:0] x1,x2,y1,y2;
-  wire DataValid;
   wire LOCKUP;
 
-  arm_soc dut(.HCLK, .HRESETn, .x1, .y1, .x2, .y2, .DataValid, .Switches, .Buttons, .LOCKUP);
+  arm_soc dut(.HCLK, .HRESETn, .x1, .y1, .x2, .y2, .Switches, .Buttons, .LOCKUP);
 
   always
     begin
-- 
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