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  • 49d5d53a · added a 12 bit input process that reads from the adc input csv test...
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  • d1f48939 · matlab file for generating 12 bit noisy samples from msf input
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  • 46d3ae7c · prints a sampled output into csv file
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  • 5c87e99a · supports day of week, day of month, month and year, added synchrono...
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  • 1c70cd05 · includes all rtc ports, fast clock for fast simulation
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  • 64e65c67 · testbench for rtc, sets time
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  • b438526a · can compile, fixed sensitivity list
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Jack Driscoll's avatar
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  • e4133d4f · added invert signal and can insert errors for parity check
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  • 775ccb99 · Update basic_msf_signal_tb.vhd
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  • b48432e7 · Update basic_msf_signal_tb.vhd
Jack Driscoll's avatar
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Jack Driscoll's avatar
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Jack Driscoll's avatar
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Jack Driscoll's avatar
pushed to branch main at Jack Driscoll / VHDL