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Jack Driscoll
VHDL
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Created with Raphaël 2.2.0
30
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added a 12 bit input process that reads from the adc input csv test vector file
main
main
matlab file for generating 12 bit noisy samples from msf input
12 bit noisy msf samples
prints a sampled output into csv file
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supports day of week, day of month, month and year, added synchronous reset
includes all rtc ports, fast clock for fast simulation
testbench for rtc, sets time
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can compile, fixed sensitivity list
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added invert signal and can insert errors for parity check
Update basic_msf_signal_tb.vhd
Update basic_msf_signal_tb.vhd
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Update 2 files
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Add new directory for testbenches
Add new directory for simple msf testbench
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