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Commit ad7756a0 authored by Jasper He's avatar Jasper He
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Zero and Infinity Check

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Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
+ 6
− 13
View file @ ad7756a0
......@@ -5,12 +5,12 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
Posit_Adder_tb
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv}
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Leading_Bit_Detector
-- Compiling module Leading_Bit_Detector_8B
Top level modules:
Leading_Bit_Detector
Leading_Bit_Detector_8B
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
......@@ -19,18 +19,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
Data_Extraction
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Leading_Bit_Detector_8B
Top level modules:
Leading_Bit_Detector_8B
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv}
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Posit_Adder
-- Compiling module Leading_Bit_Detector
Top level modules:
Posit_Adder
Leading_Bit_Detector
} {} {}}
Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
+ 9
− 9
View file @ ad7756a0
......@@ -411,16 +411,16 @@ Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 5
Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1676404420 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677028231 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677036594 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677030944 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677030944 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1677274831 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677028231 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1676404420 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677036563 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1677275421 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......
Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
+ 10
− 1
View file @ ad7756a0
......@@ -161,7 +161,16 @@ begin
//Final Output
sft_tmp_oN = LS ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
OUT = {LS, sft_tmp_oN[N-1:1]};
if (zero1)
OUT = IN2;
else if (zero2)
OUT = IN1;
else if (inf1)
OUT = IN1;
else if (inf2)
OUT = IN2;
else
OUT = {LS, sft_tmp_oN[N-1:1]};
end
endmodule
\ No newline at end of file
Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
+ 7
− 7
View file @ ad7756a0
......@@ -85,11 +85,11 @@ end
// initial
// begin
// #10ns
// IN1 = 8'b0_0000000;
// IN2 = 8'b0_0000000;
// IN1 = 8'b0_0000000;
// IN2 = 8'b0_0000000;
// IN1 = 8'b0_0000011;
// IN2 = 8'b0_0000000;
// IN1 = 8'b0_0000011;
// IN2 = 8'b0_0000000;
// #50ns // 56-10
// IN1 = 8'b01010111;
// IN2 = 8'b10110011;
......@@ -102,9 +102,9 @@ end
// IN1 = 8'b11000100;
// IN2 = 8'b01000011;
// #50ns // 56-10
// #50ns // 3-2
// IN1 = 8'b01000110;
// IN2 = 8'b11000000;
// IN2 = 8'b10111100;
// // #50ns // 56-10
// // IN1 = 8'b01010111;
......@@ -133,7 +133,7 @@ end
// #50ns // 0.125+0.15625
// IN1 = 8'b0_01_101_00;
// IN2 = 8'b0_01_101_01;
// end
// end
......
Individual_Project/Posit_Adder/Core_Arithmetic/wlft7ciyi4 0 → 100644
+ 0
− 0
View file @ ad7756a0
File added
Individual_Project/Posit_Adder/Core_Arithmetic/work/_info
+ 23
− 23
View file @ ad7756a0
......@@ -38,7 +38,7 @@ Z11 tCvgOpt 0
n@arithmetic_tb
vData_Extraction
R0
Z12 !s110 1677094499
Z12 !s110 1677275424
!i10b 1
!s100 ?M;l4a18YgFdj=6@ZQHk30
Z13 !s11b Dg1SIo80bB@j0V0VzS_@n1
......@@ -49,13 +49,13 @@ R3
w1677028231
Z14 8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
Z15 FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
!i122 323
!i122 353
L0 18 57
R6
r1
!s85 0
31
Z16 !s108 1677094499.000000
Z16 !s108 1677275424.000000
Z17 !s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv|
Z18 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv|
!i113 1
......@@ -75,7 +75,7 @@ R3
w1676404420
8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
!i122 324
!i122 354
L0 19 34
R6
r1
......@@ -116,7 +116,7 @@ R11
n@leading_@bit_@detector_8b
vLeading_Bit_Detector_8B
R0
Z19 !s110 1677094500
Z19 !s110 1677275425
!i10b 1
!s100 fzH72J8YEDz;1i]WHmSd[2
R13
......@@ -127,13 +127,13 @@ R3
w1677030944
8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
!i122 326
!i122 356
L0 19 33
R6
r1
!s85 0
31
!s108 1677094500.000000
Z20 !s108 1677275425.000000
!s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv|
!i113 1
......@@ -144,24 +144,24 @@ vPosit_Adder
R0
R19
!i10b 1
!s100 K8=gPPZmhcE6]4;0>f19>0
!s100 >IT=V<RJhPDM0;:o;0Bk<1
R13
Ih@MKDA2_k@;Zle:j8FDRE2
I_`M0mATH0bliB]a7_SGie3
R2
S1
R3
w1677036563
Z20 8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
Z21 FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
!i122 325
L0 19 149
w1677275421
Z21 8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
Z22 FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
!i122 355
L0 19 158
R6
r1
!s85 0
31
R16
Z22 !s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv|
Z23 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv|
R20
Z23 !s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv|
Z24 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv|
!i113 1
R10
R11
......@@ -182,7 +182,7 @@ w1675896509
8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv
FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv
!i122 22
Z24 L0 19 0
Z25 L0 19 0
R6
31
R7
......@@ -205,15 +205,15 @@ IO21Qg[>8O]7TDNkioZ[GV2
S1
R3
w1677014662
R20
R21
R22
!i122 47
R24
R25
R6
31
!s108 1677015825.000000
R22
R23
R24
!i113 1
R10
R11
......@@ -228,10 +228,10 @@ I]bO0fmQQ[]iWZ=MT2=hkJ3
R2
S1
R3
w1677036594
w1677274831
R4
R5
!i122 322
!i122 352
L0 19 122
R6
r1
......
Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib.qdb
+ 0
− 0
View file @ ad7756a0
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