diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
index c73f8d5e9ef6a7b4a3cdc05bcafab2e5d61b87b4..2c7a129b1f6a345ebaf54a698b616b339fa95fa0 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
@@ -5,12 +5,12 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
Posit_Adder_tb
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv}
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Leading_Bit_Detector
+-- Compiling module Leading_Bit_Detector_8B
Top level modules:
- Leading_Bit_Detector
+ Leading_Bit_Detector_8B
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
@@ -19,18 +19,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
Data_Extraction
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Leading_Bit_Detector_8B
-
-Top level modules:
- Leading_Bit_Detector_8B
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv}
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Posit_Adder
+-- Compiling module Leading_Bit_Detector
Top level modules:
- Posit_Adder
+ Leading_Bit_Detector
} {} {}}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
index 9a8724888ba5d35da54e8176cc63ab66dd3598f7..3cc32b594d2e8fb74aa5d39fc96ad07f580788d6 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
@@ -411,16 +411,16 @@ Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 5
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1676404420 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677028231 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
-Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677036594 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
-Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677030944 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677030944 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1677274831 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677028231 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1676404420 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
-Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677036563 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1677275421 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
index 09c4f7ae9cea55266e3a2fff372ce5a618a46b4d..3e49defe875eec8b691551839f0325dd09a584be 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
@@ -161,7 +161,16 @@ begin
//Final Output
sft_tmp_oN = LS ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
- OUT = {LS, sft_tmp_oN[N-1:1]};
+ if (zero1)
+ OUT = IN2;
+ else if (zero2)
+ OUT = IN1;
+ else if (inf1)
+ OUT = IN1;
+ else if (inf2)
+ OUT = IN2;
+ else
+ OUT = {LS, sft_tmp_oN[N-1:1]};
end
endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
index ca398b879d5e36304870b02b06912667486bcb21..efd9d58f7fae2f579812bf2f45bd587207f7cf8d 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
@@ -85,11 +85,11 @@ end
// initial
// begin
// #10ns
- // IN1 = 8'b0_0000000;
- // IN2 = 8'b0_0000000;
+// IN1 = 8'b0_0000000;
+// IN2 = 8'b0_0000000;
- // IN1 = 8'b0_0000011;
- // IN2 = 8'b0_0000000;
+// IN1 = 8'b0_0000011;
+// IN2 = 8'b0_0000000;
// #50ns // 56-10
// IN1 = 8'b01010111;
// IN2 = 8'b10110011;
@@ -102,9 +102,9 @@ end
// IN1 = 8'b11000100;
// IN2 = 8'b01000011;
-// #50ns // 56-10
+// #50ns // 3-2
// IN1 = 8'b01000110;
-// IN2 = 8'b11000000;
+// IN2 = 8'b10111100;
// // #50ns // 56-10
// // IN1 = 8'b01010111;
@@ -133,7 +133,7 @@ end
// #50ns // 0.125+0.15625
// IN1 = 8'b0_01_101_00;
// IN2 = 8'b0_01_101_01;
- // end
+// end
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt
index 658be9c7743cc4f76e73bd7508b0736140c303b7..533669de77b07b91e8c2d80bf211cb854efa5916 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt
@@ -1,4 +1,3 @@
- 68
0
0
0
@@ -62,22 +61,8 @@
0
0
0
- 4
- 3
- 3
- 3
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
0
- 1
0
- 1
0
0
0
@@ -125,9 +110,6 @@
0
0
0
- 1
- 64
- 1
0
0
0
@@ -178,19 +160,37 @@
0
0
0
- 1
- 1
- 1
- 1
- 2
- 2
- 2
- 3
- 4
- 5
- 6
- 9
- 28
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
0
0
0
@@ -382,7 +382,7 @@
0
0
1
-128
+ 0
1
0
0
@@ -638,7 +638,7 @@
0
0
1
-126
+ 0
1
0
0
@@ -1150,7 +1150,7 @@
0
0
1
-124
+ 0
1
0
0
@@ -1406,7 +1406,7 @@
0
0
1
-123
+ 0
1
0
0
@@ -1662,7 +1662,7 @@
0
0
1
-122
+ 0
1
0
0
@@ -1918,7 +1918,7 @@
0
0
1
-121
+ 0
1
0
0
@@ -2174,7 +2174,7 @@
0
0
1
-120
+ 0
1
0
0
@@ -2430,7 +2430,7 @@
0
0
1
-119
+ 0
1
0
0
@@ -2686,7 +2686,7 @@
0
0
1
-118
+ 0
1
0
0
@@ -2942,7 +2942,7 @@
0
0
1
-117
+ 0
1
0
0
@@ -3198,7 +3198,7 @@
0
0
1
-116
+ 0
1
0
0
@@ -3454,7 +3454,7 @@
0
0
1
-115
+ 0
1
0
0
@@ -3710,7 +3710,7 @@
0
0
1
-114
+ 0
1
0
0
@@ -3966,7 +3966,7 @@
0
0
1
-113
+ 0
1
0
0
@@ -4222,7 +4222,7 @@
0
0
1
-112
+ 0
1
0
0
@@ -4478,7 +4478,7 @@
0
0
1
-111
+ 0
1
0
0
@@ -4734,7 +4734,7 @@
0
0
1
-110
+ 0
1
0
0
@@ -4990,7 +4990,7 @@
0
0
1
-109
+ 0
1
0
0
@@ -5246,7 +5246,7 @@
0
0
1
-108
+ 0
1
0
0
@@ -5502,7 +5502,7 @@
0
0
1
-107
+ 0
1
0
0
@@ -5758,7 +5758,7 @@
0
0
1
-106
+ 0
1
0
0
@@ -6014,7 +6014,7 @@
0
0
1
-105
+ 0
1
0
0
@@ -6270,7 +6270,7 @@
0
0
1
-104
+ 0
1
0
0
@@ -6526,7 +6526,7 @@
0
0
1
-103
+ 0
1
0
0
@@ -6782,7 +6782,7 @@
0
0
1
-102
+ 0
1
0
0
@@ -7038,7 +7038,7 @@
0
0
1
-101
+ 0
1
0
0
@@ -7294,7 +7294,7 @@
0
0
1
-100
+ 0
1
0
0
@@ -7550,7 +7550,7 @@
0
0
1
- 99
+ 0
1
0
0
@@ -7806,7 +7806,7 @@
0
0
1
- 98
+ 0
1
0
0
@@ -8062,7 +8062,7 @@
0
0
1
- 97
+ 0
1
0
0
@@ -8318,7 +8318,7 @@
0
0
1
- 96
+ 0
1
0
0
@@ -8574,7 +8574,7 @@
0
0
1
- 95
+ 0
1
0
0
@@ -8830,7 +8830,7 @@
0
0
1
- 94
+ 0
1
0
0
@@ -9086,7 +9086,7 @@
0
0
1
- 93
+ 0
1
0
0
@@ -9342,7 +9342,7 @@
0
0
1
- 92
+ 0
1
0
0
@@ -9598,7 +9598,7 @@
0
0
1
- 91
+ 0
1
0
0
@@ -9854,7 +9854,7 @@
0
0
1
- 90
+ 0
1
0
0
@@ -10110,7 +10110,7 @@
0
0
1
- 89
+ 0
1
0
0
@@ -10366,7 +10366,7 @@
0
0
1
- 88
+ 0
1
0
0
@@ -10622,7 +10622,7 @@
0
0
1
- 87
+ 0
1
0
0
@@ -10878,7 +10878,7 @@
0
0
1
- 86
+ 0
1
0
0
@@ -11134,7 +11134,7 @@
0
0
1
- 85
+ 0
1
0
0
@@ -11390,7 +11390,7 @@
0
0
1
- 84
+ 0
1
0
0
@@ -11646,7 +11646,7 @@
0
0
1
- 83
+ 0
1
0
0
@@ -11902,7 +11902,7 @@
0
0
1
- 82
+ 0
1
0
0
@@ -12158,7 +12158,7 @@
0
0
1
- 81
+ 0
1
0
0
@@ -12414,7 +12414,7 @@
0
0
1
- 80
+ 0
1
0
0
@@ -12670,7 +12670,7 @@
0
0
1
- 79
+ 0
1
0
0
@@ -12926,7 +12926,7 @@
0
0
1
- 78
+ 0
1
0
0
@@ -13182,7 +13182,7 @@
0
0
1
- 77
+ 0
1
0
0
@@ -13438,7 +13438,7 @@
0
0
1
- 76
+ 0
1
0
0
@@ -13694,7 +13694,7 @@
0
0
1
- 75
+ 0
1
0
0
@@ -13950,7 +13950,7 @@
0
0
1
- 74
+ 0
1
0
0
@@ -14206,7 +14206,7 @@
0
0
1
- 73
+ 0
1
0
0
@@ -14462,7 +14462,7 @@
0
0
1
- 72
+ 0
1
0
0
@@ -14718,7 +14718,7 @@
0
0
1
- 71
+ 0
1
0
0
@@ -14974,7 +14974,7 @@
0
0
1
- 70
+ 0
1
0
0
@@ -15230,7 +15230,7 @@
0
0
1
- 69
+ 0
1
0
0
@@ -15486,7 +15486,7 @@
0
0
1
- 68
+ 0
1
0
0
@@ -15742,7 +15742,7 @@
0
0
1
- 67
+ 0
1
0
0
@@ -15998,7 +15998,7 @@
0
0
1
- 66
+ 0
1
0
0
@@ -16254,7 +16254,7 @@
0
0
1
- 65
+ 0
1
0
0
@@ -16382,7 +16382,7 @@
0
0
0
- 4
+ 0
0
0
0
@@ -16510,7 +16510,7 @@
0
0
1
- 64
+ 0
1
0
0
@@ -16638,7 +16638,7 @@
0
0
0
- 3
+ 0
0
0
0
@@ -16766,7 +16766,7 @@
0
0
1
- 63
+ 0
1
0
0
@@ -16894,7 +16894,7 @@
0
0
0
- 3
+ 0
0
0
0
@@ -17022,7 +17022,7 @@
0
0
1
- 62
+ 0
1
0
0
@@ -17150,7 +17150,7 @@
0
0
0
- 3
+ 0
0
0
0
@@ -17278,7 +17278,7 @@
0
0
1
- 61
+ 0
1
0
0
@@ -17406,7 +17406,7 @@
0
0
0
- 2
+ 0
0
0
0
@@ -17534,7 +17534,7 @@
0
0
1
- 60
+ 0
1
0
0
@@ -17662,7 +17662,7 @@
0
0
0
- 2
+ 0
0
0
0
@@ -17790,7 +17790,7 @@
0
0
1
- 59
+ 0
1
0
0
@@ -17918,7 +17918,7 @@
0
0
0
- 2
+ 0
0
0
0
@@ -18046,7 +18046,7 @@
0
0
1
- 58
+ 0
1
0
0
@@ -18174,7 +18174,7 @@
0
0
0
- 1
+ 0
0
0
0
@@ -18302,7 +18302,7 @@
0
0
1
- 57
+ 0
1
0
0
@@ -18430,7 +18430,7 @@
0
0
0
- 1
+ 0
0
0
0
@@ -18558,7 +18558,7 @@
0
0
1
- 56
+ 0
1
0
0
@@ -18686,7 +18686,7 @@
0
0
0
- 1
+ 0
0
0
0
@@ -18814,7 +18814,7 @@
0
0
1
- 55
+ 0
1
0
0
@@ -18942,7 +18942,7 @@
0
0
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