Finished Adder

Individual_Project/Core_Arithmetic/Arithmetic.cr.mti

-{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Leading_Bit_Detector_8b.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Leading_Bit_Detector_8b.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Leading_Bit_Detector_8b
 
-Top level modules:
-	Leading_Bit_Detector_8b
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling package Posit_Adder_Arithmetic_sv_unit
--- Compiling module Alignment
-
-Top level modules:
-	Alignment
-
-} {} {}}

Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv

@@ -10,8 +10,8 @@
 //            : 
 // System     : SystemVerilog IEEE 1800-2005
 //            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
+// Author     : Xiaoan(Jasper) He 
+//            : xh2g20@soton.ac.uk
 //
 // Revision   : Version 1.0 01/12/2022
 /////////////////////////////////////////////////////////////////////
@@ -37,15 +37,17 @@ module Alignment #(parameter N = 8, parameter ES = 3, parameter RS = log2(N))
     output logic signed [ES+RS:0] LE_O,
     output logic [ES-1:0] E_O,
     output logic signed [RS:0] R_O,
-    output logic signed [N-1:0] Result
+    output logic signed [N-1:0] Result,
+    output logic signed [N-1:0] out
 );
     logic Operation;
     // components to corresponding logic, L - Large S - Small
+    logic signed [N-2:0] LIn, SIn;
     logic LS, SS;
     logic [RS:0] LR, SR;
     logic LRC, SRC;
     logic [ES-1:0]LE, SE;
-    logic [N:0]LM, SM, SM_tmp;
+    logic [N-1:0]LM, SM, SM_tmp;
     // logic SS;
     // logic [RS:0]SR;
     // logic SRC;
@@ -59,7 +61,15 @@ module Alignment #(parameter N = 8, parameter ES = 3, parameter RS = log2(N))
     logic [ES+RS:0] LE_ON;
     logic [N-1:0] RegimeBits;
     //Leading_Bit_Detector_8b #(.N(N), .ES(ES)) LBD_Mant (.*);
-    logic [N-1:0] ONEs;
+    //logic [N-1:0] ONEs;
+    logic [(2*N-1)+3:0] tmp_o;
+    logic [(3*N-1)+3:0] sft_tmp_o;
+
+    logic L,G,R,S,ulp;
+    logic [N-1:0] rnd_ulp; 
+    logic [N:0] sft_tmp_o_rnd_ulp;
+    logic [N-1:0] sft_tmp_o_rnd;
+    logic [N-1:0] sft_tmp_oN;
 
 always_comb
 begin
@@ -70,16 +80,20 @@ begin
     // Find the greater input
     Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
     // Assign components to corresponding logic, L - Large S - Small
+    LIn = Greater_Than ? InRemain1 : InRemain2;
     LS = Greater_Than ? Sign1 : Sign2;
     LR = Greater_Than ? RegimeValue1 : RegimeValue2;
     LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
     LE = Greater_Than ? Exponent1 : Exponent2;
-    LM = Greater_Than ? {1'b0, Mantissa1} : {1'b0,Mantissa2};
-
+    LM = Greater_Than ? Mantissa1 : Mantissa2; // the first bit (0) is reserved for overflow detection
+    
+    SIn = Greater_Than ? InRemain2 : InRemain1;
     SS = Greater_Than ? Sign2 : Sign1;
     SR = Greater_Than ? RegimeValue2 : RegimeValue1;
+    LRC = Greater_Than? InRemain2[N-2] : InRemain1[N-2];
     SE = Greater_Than ? Exponent2 : Exponent1;
-    SM = Greater_Than ? {1'b0, Mantissa2} : {1'b0,Mantissa1};
+    SM = Greater_Than ? Mantissa2 : Mantissa1;
+
 
     // Mantissa Addition
     /*
@@ -95,7 +109,7 @@ begin
     //     R_diff = RegimeValue1 - RegimeValue2;
     // else if (RegimeValue1 < 0 && RegimeValue2 < 0)
     //     R_diff = RegimeValue1 - RegimeValue2;
-    R_diff = RegimeValue1 - RegimeValue2;
+    R_diff = LR - SR;
 
     /*
     after the R_diff found, remember that the regime contributes into the exponent
@@ -130,40 +144,77 @@ begin
     The exponent is mainly based on the larger input
     taking overflow and left shift into account
     */
-    LE_O = {LR, LE} + Mant_Ovf; //- shift;
+    // LE_O = {LR, LE} + Mant_Ovf; //- shift;
+    // LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
     
+    LE_O = {LR, LE} + Mant_Ovf; //- shift;
     LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
-    /*
-        if LE_O is -ve and Least Significant ES bits of LE_ON is non zero
-        E_O is 2's complement of Least Significant ES bits of LE_ON
-        if LE_O is positive, E_O = LSB ES bits of LE_O    
-    */
-    if (!LE_O[ES+RS])
-        E_O = LE_O[ES-1:0];
-    else if (|LE_ON[ES-1:0])
-        E_O = LE_O[ES-1:0];
-    else
-        E_O = LE_ON[ES-1:0];
-    /*  
-        if LE_O is +ve OR LE_O is -ve and LSB ES bits of LE_ON is non zero
-        R_O = 
-    */
-    //R_O = LE_O[ES+RS:ES];
-    if (!LE_O[ES+RS])
-        R_O = LE_ON[ES+RS-1 : ES];
-    else if ((LE_O[ES+RS]&(|LE_ON[ES-1 : 0])))
-        R_O =  (LE_ON[ES+RS-1 : ES] +1'b1);
+
+    E_O = LE_O[ES-1:0];
+
+    R_O = (~LE_O[ES+RS] || |(LE_ON[ES-1:0])) ? LE_ON[ES+RS-1:ES] + 1 : LE_ON[ES+RS-1:ES];
+
+    // if(!LE_O[ES+RS])
+    //     begin
+    //     E_O = LE_O[ES-1:0];
+    //     R_O = LE_O[ES+RS:ES];
+    //     end
+    // else 
+    //     begin 
+    //     LE_ON = -LE_O;
+    //     if(|LE_ON[ES-1:0])
+    //         begin
+    //         E_O = LE_ON[ES-1:0];
+    //         R_O = LE_ON[ES+RS:ES]+1;
+    //         end
+    //     else   
+    //         begin
+    //         E_O = LE_O[ES-1:0];
+    //         R_O = LE_ON[ES+RS:ES];
+    //         end
+    //     end
+
+    //tmp_o = { {N{~LE_O[ES+RS]}}, LE_O[ES+RS], E_O, Add_Mant[N-1:((N-1)-(2N-N-1-ES))], 3'b0 };
+    tmp_o = { {N{~LE_O[ES+RS]}}, LE_O[ES+RS], E_O, Add_Mant[(N-1):(N-(2*N-N-1-ES))], 3'b0 };
+    sft_tmp_o = {tmp_o, 8'b0} ;
+    sft_tmp_o = sft_tmp_o>> R_O;
+
+    L = sft_tmp_o[N+4]; 
+    G = sft_tmp_o[N+3]; 
+    R = sft_tmp_o[N+2]; 
+    S = |sft_tmp_o[N+1:0];
+    ulp = ((G & (R | S)) | (L & G & ~(R | S)));
+    
+    rnd_ulp= {{N-1{1'b0}},ulp};
+
     
-    // Post Processing
-    ONEs = '1;
-    if (!R_O[RS])
-    RegimeBits = ONEs << (8-1-R_O);
-    else
-    RegimeBits = ONEs >> (8-R_O);
-
-    // RB_tmp = RegimeBits[N-1:N-(R_O+2)];
+    sft_tmp_o_rnd_ulp = sft_tmp_o[2*N-1+3:N+3] + rnd_ulp;
+
+    
+    sft_tmp_o_rnd = (R_O < N-ES-2) ? sft_tmp_o_rnd_ulp[N-1:0] : sft_tmp_o[2*N-1+3:N+3];
+
+
+    //Final Output
     
-    // Result = {LS, RB_tmp, E_O};
+    sft_tmp_oN = LS ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
+    out = {LS, sft_tmp_oN[N-1:1]};
+    //out = inf|zero|(~DSR_left_out[N-1]) ? {inf,{N-1{1'b0}}} : {ls, sft_tmp_oN[N-1:1]};
+
+    // /*
+    //     if LE_O is -ve and Least Significant ES bits of LE_ON is non zero
+    //     E_O is 2's complement of Least Significant ES bits of LE_ON
+    //     if LE_O is positive, E_O = LSB ES bits of LE_O    
+    // */
+   
+    // /*  
+    //     if LE_O is +ve OR LE_O is -ve and LSB ES bits of LE_ON is non zero
+    //     R_O = 
+    // */
+    // //R_O = LE_O[ES+RS:ES];
+    // if (!LE_O[ES+RS])
+    //     R_O = LE_ON[ES+RS-1 : ES];
+    // else if ((LE_O[ES+RS]&(|LE_ON[ES-1 : 0])))
+    //     R_O =  (LE_ON[ES+RS-1 : ES] +1'b1);
 
 end
 endmodule
\ No newline at end of file

posit_adder_verilog/Test.cr.mti

-{H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add_8bit_tb.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add_8bit_tb.v}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module posit_add_8bit_tb_v
-
-Top level modules:
-	posit_add_8bit_tb_v
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add.v}
+{H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/posit_adder_verilog/posit_add.v}
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module posit_add
 -- Compiling module data_extract_v1