Data Extraction Debugged

Individual_Project/Data Extraction/Data_Extraction.cr.mti

+{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv}
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling package Posit_Extraction_sv_unit
+-- Compiling module Data_Extraction
+
+Top level modules:
+	Data_Extraction
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv}
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Leading_Bit_Detector
+
+Top level modules:
+	Leading_Bit_Detector
+
+} {} {}}

Individual_Project/Data Extraction/Leading_Bit_Detector.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Leading Bit Detector
+//            :
+// File name  : Leading_Bit_Detector.sv
+//            :
+// Description: Given the first bit of the regime bit
+//              find the first bit different from it
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+
+module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+    input logic signed [N-2:0] InRemain,
+    output logic signed [RS:0] EndPosition,
+    output logic RegimeCheck
+);
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+//logic RegimeCheck; 
+int i;
+
+always_comb
+begin
+    RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
+    
+    EndPosition = '0;
+    EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+
+    for(i = 1; i < (N-2); i++) 
+        begin
+            /* 
+            compareing MSB of InRemain to the follwing bits
+            until the different bit turns up    
+            */
+            if (RegimeCheck == InRemain[((N-2)-i)])
+                //begin
+                EndPosition = EndPosition + 1'b1;
+                //end
+            else 
+                break;
+        end
+
+end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/Posit_Extraction.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: DataExtraction
+//            :
+// File name  : Posit_Extraction.sv
+//            :
+// Description: Extracting posit element from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 19/11/2022
+/////////////////////////////////////////////////////////////////////
+
+// `ifndef log_2
+// `define log_2
+// `include "log_2.sv"
+
+function [31:0] log2;
+    input reg [31:0] value;
+        begin
+            value = value-1;
+            for (log2=0; value>0; log2=log2+1)
+                value = value>>1;
+        end
+endfunction
+
+module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+    input logic signed [N-1:0] In,
+    output logic Sign,
+    output logic signed [RS-1:0] RegimeValue,
+    output logic [ES-1:0] Exponent,
+    output logic [N-ES+2:0] Mantissa
+);
+
+logic signed [N-2:0] InRemain;
+logic RegimeCheck; 
+logic [RS:0] EndPosition;
+logic signed [N-2:0] ShiftedRemain;
+int i;
+Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
+
+always_comb
+begin
+    // Sign Bit Extraction
+    Sign = In[N-1];
+    // if sign bit is true, then 2's compliment
+    InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0];
+
+    // Regime Bits Extraction
+    
+
+    if(RegimeCheck == 1'b1)
+        RegimeValue = EndPosition - 1;
+    else if (RegimeCheck == 0)
+        RegimeValue = -EndPosition;
+
+    //Exponent Bits Extraction
+    ShiftedRemain = InRemain << (EndPosition + 1 );
+    Exponent = ShiftedRemain[N-1:((N-1)-ES)];
+
+    //Mantissa Bits Extraction
+    Mantissa = {1'b1, ShiftedRemain[N-ES-2]};
+end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/Test_Data_Extraction.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: TestDataExtraction
+//            :
+// File name  : testExtract.sv
+//            :
+// Description: Testbench for extracting posit element 
+//              from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+module Test_Data_Extraction;
+parameter N = 8, RS = log2(N), ES = 3;
+
+//input logic
+logic signed [N-1:0]In;
+
+//output logic
+logic Sign;
+logic signed [RS:0] RegimeValue;
+logic [ES-1:0] Exponent;
+logic [N-ES+2:0] Mantissa;
+
+Data_Extraction #(.N(N), .ES(ES)) extract1 (.*);
+
+initial
+    begin
+        // initial input is nothing
+        #10ns In = 8'b0_0000000;
+        // sign=0 regime=10 exponent=1001,mant=1    
+        #50ns In = 8'b1_01_1000_0;  
+        // 0_10_1000_0
+    end
+endmodule
\ No newline at end of file

Individual_Project/Data Extraction/log_2.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Logarithm Base 2
+//            :
+// File name  : log_2.sv
+//            :
+// Description: Just be used to compute the Regime Size (RS)
+//            : which is equal to log2(the number of total bits)
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 19/11/2022
+/////////////////////////////////////////////////////////////////////
+
+#ifndef log_2
+#define log_2
+
+function [31:0] log2;
+input logic [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
\ No newline at end of file

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Individual_Project/Data Extraction/work/_vmake

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Individual_Project/Posit_Extraction.sv

@@ -28,49 +28,54 @@ function [31:0] log2;
         end
 endfunction
 
-Module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
 (
     input logic signed [N-1:0] In,
     output logic Sign,
-    output logic signed [RS-1:0] Regime,
+    output logic signed [RS-1:0] RegimeValue,
     output logic [ES-1:0] Exponent,
     output logic [N-ES+2:0] Mantissa
-)
+);
 
-// Sign Bit Extraction
-logic signed [N-2:0] InRemain;
+always_comb
+begin
+    // Sign Bit Extraction
+    logic signed [N-2:0] InRemain;
 
-Sign = In[N-1];
-if(Sign = 1)    // if sign bit is 1, then 2's compliment
-    InRemain = ~In[N-2:0] + 1'b1;
-else
-    InRemain = In[N-2:0];
+    Sign = In[N-1];
+    if(Sign = 1)    // if sign bit is 1, then 2's compliment
+        InRemain = ~In[N-2:0] + 1'b1;
+    else
+        InRemain = In[N-2:0];
 
-// Regime Bits Extraction
-logic RegimeCheck = InRemain{N-2}; //the MSB of InRemain is the number to be checked
+    // Regime Bits Extraction
+    logic RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
 
-logic [RS-1:0] EndPosition = 1; // initial EP starts from 2nd element
+    logic [RS-1:0] EndPosition = 1; // initial EP starts from InRemain[1] as InRemain[0] is RC
 
-for(int i = 1; i < N-2; i++)
-    begin
-        /* 
-        compareing MSB of InRemain to the follwing bits
-        until the different bit turns up    
-        */
-        if(RegimeCheck == InRemain[((N-2)-i)])
-            EndPosition = EndPositon + 1;
-        else 
-            break;
-    end
+    for(int i = 1; i < N-2; i++)
+        begin
+            /* 
+            compareing MSB of InRemain to the follwing bits
+            until the different bit turns up    
+            */
+            if(RegimeCheck == InRemain[((N-2)-i)])
+                EndPosition = EndPositon + 1;
+            else 
+                break;
+        end
 
-// logic RegimeValue;
+    if(RegimeCheck == 1)
+        RegimeValue = EndPosition - 1;
+    else if (RegimeCheck == 0)
+        RegimeValue = -EndPositon;
 
-// if(RegimeCheck = 1)
-//     RegimeValue = EndPosition - 1;
-// else
-//     RegimeValue = -EndPositon;
+    //Exponent Bits Extraction
+    logic signed [N-2:0] ShiftedRemain;
+    ShiftedRemain = InRemain << (EndPosition + 1 );
+    Exponent = ShiftedRemain[N-1:((N-1)-ES)];
 
-// Exponent Bits Extraction
-logic signed [N-2:0] ShiftedRemain;
-ShiftedRemain = InRemain << (EndPosition + )
+    //Mantissa Bits Extraction
+    Mantissa = {1'b1, ShiftedRemain[N-ES-2]};
+end
 endmodule
\ No newline at end of file

Individual_Project/testExtract.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: TestDataExtraction
+//            :
+// File name  : testExtract.sv
+//            :
+// Description: Testbench for extracting posit element 
+//              from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 14/11/2022
+/////////////////////////////////////////////////////////////////////
+
+module testExtract;
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+parameter N = 8, Bs = log2(N), es = 3;
+
+//input logic
+logic signed [N-1:0]In;
+//output logic
+logic Sign;
+logic [ES-1:0]Exponent;
+logic signed [Es-1:0]Regime;
+logic [N-ES+2:0]Mantissa;
+
+Data_Extraction extract1 (.*);
+
+initial
+    begin
+        // initial input is nothing
+        #10ns in = 8'b0_0000000;
+        // sign=0 regime=10 exponent=1001,mant=1    
+        #50ns in = 8'b1_01_1000_0;  
+        // 0_10_1000_0
+    end
+
+endmodule
\ No newline at end of file

posit_adder_sv/data_extract.sv

-module data_extract #(parameter N=8, parameter Bs=log2(N), parameter es=4, parameter Rmax = N-1, parameter Rmin = -(N-1))
+module data_extract #(parameter N=8, parameter Bs=log2(N), 
+parameter es=4, parameter Rmax = N-1, parameter Rmin = -(N-1))
 (input logic signed [N-1:0] in,
 output logic Sin,
 output logic [es-1:0] exp,