Posit Adder Extraction

Individual_Project/Posit_Extraction.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: DataExtraction
+//            :
+// File name  : Posit_Extraction.sv
+//            :
+// Description: Extracting posit element from n bits binary number
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 19/11/2022
+/////////////////////////////////////////////////////////////////////
+
+// `ifndef log_2
+// `define log_2
+// `include "log_2.sv"
+
+function [31:0] log2;
+    input reg [31:0] value;
+        begin
+            value = value-1;
+            for (log2=0; value>0; log2=log2+1)
+                value = value>>1;
+        end
+endfunction
+
+Module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+    input logic signed [N-1:0] In,
+    output logic Sign,
+    output logic signed [RS-1:0] Regime,
+    output logic [ES-1:0] Exponent,
+    output logic [N-ES+2:0] Mantissa
+)
+
+// Sign Bit Extraction
+logic signed [N-2:0] InRemain;
+
+Sign = In[N-1];
+if(Sign = 1)    // if sign bit is 1, then 2's compliment
+    InRemain = ~In[N-2:0] + 1'b1;
+else
+    InRemain = In[N-2:0];
+
+// Regime Bits Extraction
+logic RegimeCheck = InRemain{N-2}; //the MSB of InRemain is the number to be checked
+
+logic [RS-1:0] EndPosition = 1; // initial EP starts from 2nd element
+
+for(int i = 1; i < N-2; i++)
+    begin
+        /* 
+        compareing MSB of InRemain to the follwing bits
+        until the different bit turns up    
+        */
+        if(RegimeCheck == InRemain[((N-2)-i)])
+            EndPosition = EndPositon + 1;
+        else 
+            break;
+    end
+
+// logic RegimeValue;
+
+// if(RegimeCheck = 1)
+//     RegimeValue = EndPosition - 1;
+// else
+//     RegimeValue = -EndPositon;
+
+// Exponent Bits Extraction
+logic signed [N-2:0] ShiftedRemain;
+ShiftedRemain = InRemain << (EndPosition + )
+endmodule
\ No newline at end of file

Individual_Project/log_2.sv

+/////////////////////////////////////////////////////////////////////
+// Design unit: Logarithm Base 2
+//            :
+// File name  : log_2.sv
+//            :
+// Description: Just be used to compute the Regime Size (RS)
+//            : which is equal to log2(the number of total bits)
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan He (Jasper)
+//            : xh2g20@ecs.soton.ac.uk
+//
+// Revision   : Version 1.0 19/11/2022
+/////////////////////////////////////////////////////////////////////
+
+#ifndef log_2
+#define log_2
+
+function [31:0] log2;
+input logic [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
\ No newline at end of file

posit_adder_verilog/README.txt

+File description:
+1. posit_add.v 			: Top-module which takes N (posit word size) and es (posit exponent size). It also contains all the required sub-module. 
+
+Below are the files for test-module for posit adder with N=8, ES=4 (User can test for other options). It is an all exhaustive test for 8-bit operands.
+
+2. posit_add_8bit_tb.v		: Test-bench module. 	
+3. posit_add_8bit.sh		: A ModelSim bash script to invoke and run modelsim simulator to run the test-bench.
+4. Pin1_8bit.txt		: Input-1 8-bit 	 
+5. Pin2_8bit.txt 		: Input-2 8-bit
+6. Pout_8bit_ES4.txt		: Pre-stored posit addition results for comparison purpose. 
+
+**. error_8bit.txt		: File will be generated during simulation which contains the difference of result produce by the Verilog module with pre-stored posit addition results. 
+
+
+7. julia_posit8_add.sh		: This is a bash shell script for posit addition using julia posit package. It is currently using 8-bit inputs. Julia posit package can be downloaded from https://github.com/interplanetary-robot/SigmoidNumbers

posit_adder_verilog/add.cr.mti

+{H:/Msc project/add/posit_add_8bit_tb.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add_8bit_tb.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add_8bit_tb_v
+
+Top level modules:
+	posit_add_8bit_tb_v
+
+} {} {}} {H:/Msc project/add/posit_add.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add
+-- Compiling module data_extract_v1
+-- Compiling module sub_N
+-- Compiling module add_N
+-- Compiling module sub_N_in
+-- Compiling module add_N_in
+-- Compiling module add_sub_N
+-- Compiling module add_1
+-- Compiling module abs_regime
+-- Compiling module conv_2c
+-- Compiling module reg_exp_op
+-- Compiling module DSR_left_N_S
+-- Compiling module DSR_right_N_S
+-- Compiling module LOD_N
+-- Compiling module LOD
+
+Top level modules:
+	posit_add
+
+} {} {}}

posit_adder_verilog/adde.cr.mti

+{H:/Msc project/add/posit_add_8bit_tb.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add_8bit_tb.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add_8bit_tb_v
+
+Top level modules:
+	posit_add_8bit_tb_v
+
+} {} {}} {H:/Msc project/add/posit_add.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add
+-- Compiling module data_extract_v1
+-- Compiling module sub_N
+-- Compiling module add_N
+-- Compiling module sub_N_in
+-- Compiling module add_N_in
+-- Compiling module add_sub_N
+-- Compiling module add_1
+-- Compiling module abs_regime
+-- Compiling module conv_2c
+-- Compiling module reg_exp_op
+-- Compiling module DSR_left_N_S
+-- Compiling module DSR_right_N_S
+-- Compiling module LOD_N
+-- Compiling module LOD
+
+Top level modules:
+	posit_add
+
+} {} {}}

posit_adder_verilog/adder.cr.mti

+{H:/Msc project/add/posit_add_8bit_tb.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add_8bit_tb.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add_8bit_tb_v
+
+Top level modules:
+	posit_add_8bit_tb_v
+
+} {} {}} {H:/Msc project/add/posit_add.v} {1 {vlog -work work -vopt -stats=none {H:/Msc project/add/posit_add.v}
+Model Technology ModelSim SE-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020
+-- Compiling module posit_add
+-- Compiling module data_extract_v1
+-- Compiling module sub_N
+-- Compiling module add_N
+-- Compiling module sub_N_in
+-- Compiling module add_N_in
+-- Compiling module add_sub_N
+-- Compiling module add_1
+-- Compiling module abs_regime
+-- Compiling module conv_2c
+-- Compiling module reg_exp_op
+-- Compiling module DSR_left_N_S
+-- Compiling module DSR_right_N_S
+-- Compiling module LOD_N
+-- Compiling module LOD
+
+Top level modules:
+	posit_add
+
+} {} {}}

posit_adder_verilog/julia_posit8_add.sh

+#!/bin/bash
+
+function posit_add(y1,y2)
+		P=PS(y1)+PS(y2)
+		print(PS(y1),"\t")
+		print(PS(y2),"\t")
+		println(P)
+end
+
+if ARGS[1] == "--help"
+	println("Usgae: julia julia_posit8_add.sh N<size of operands> es<Exp size>")
+else
+	using SigmoidNumbers
+	N = parse(ARGS[1])
+	es = parse(ARGS[2])
+	PS=Posit{N,es}
+	f1=open("Pin1_8bit.txt")
+	f2=open("Pin2_8bit.txt")
+	lines1 = readlines(f1)
+	lines2 = readlines(f2)
+	for l = 1:65536
+		x1="0b"lines1[l]
+		x2="0b"lines2[l]
+		y1=parse(x1)
+		y2=parse(x2)
+		posit_add(y1,y2)
+	end
+end
+
+

posit_adder_verilog/posit_add_8bit.sh

+vlib work
+
+#All the verilog modules
+vlog "posit_add_8bit_tb.v" 
+vlog "posit_add.v"
+
+vsim -t ps work.posit_add_8bit_tb_v
+view wave
+#add wave *
+run -all

posit_adder_verilog/posit_add_8bit_tb.v

+`timescale 1ns / 1ps
+module posit_add_8bit_tb_v;
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+parameter N=8;
+parameter Bs=log2(N);
+parameter es=4;
+
+reg [N-1:0] in1, in2;
+reg start; 
+wire out_s;
+wire [Bs-1:0] out_r;
+wire [Bs+es-1:0]out_e;
+wire [N-1:0] out_m, out;
+wire done;
+
+	reg clk;
+	integer outfile;
+
+
+// Instantiate the Unit Under Test (UUT)
+posit_add #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);
+
+reg [N-1:0] data1 [1:65536];
+reg [N-1:0] data2 [1:65536];
+initial $readmemb("Pin1_8bit.txt",data1);
+initial $readmemb("Pin2_8bit.txt",data2);
+
+reg [15:0] i;
+	
+	initial begin
+		// Initialize Inputs
+		in1 = 0;
+		in2 = 0;
+		clk = 0;
+		start = 0;
+	
+		
+		// Wait 100 ns for global reset to finish
+		#100 i=0;
+		#20 start = 1;
+                #655500 start = 0;
+		#100;
+		
+		$fclose(outfile);
+		$finish;
+	end
+	
+ always #5 clk=~clk;
+
+  always @(posedge clk) begin			
+ 	in1=data1[i];	
+	in2=data2[i];
+	if(i==16'hffff)
+  	      $finish;
+	else i = i + 1;
+ end
+
+initial outfile = $fopen("error_8bit.txt", "wb");
+
+reg [N-1:0] result [1:65536];
+initial $readmemb("Pout_8bit_ES4.txt",result);
+reg [N-1:0] diff;
+always @(negedge clk) begin
+	if(start)begin
+     	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];
+     	//$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\n",in1, in2, out,result[i-1],diff);
+     	$fwrite(outfile, "%d\n",diff);
+     	end
+end
+endmodule
+

posit_adder_verilog/transcript

+# ** Error: Acs sdne.
+# 
+#        Unable to replace existing ini file (H:/Msc project/floating point 32 adder/adder.mpf).  File can not be renamed.
+# Compile of fpadder.sv was successful.
+# Compile of fpadder_tb.sv was successful.
+# 2 compiles, 0 failed with no errors.
+vsim -voptargs=+acc work.floatadd_tb
+# vsim -voptargs="+acc" work.floatadd_tb 
+# Start time: 16:16:29 on Sep 03,2022
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Note: (vopt-143) Recognized 1 FSM in module "fpadder(fast)".
+# Loading sv_std.std
+# Loading work.floatadd_tb(fast)
+# Loading work.fpadder(fast)
+add wave -position end  sim:/floatadd_tb/floatadd_test/start
+add wave -position end  sim:/floatadd_tb/floatadd_test/zerocheck
+add wave -position end  sim:/floatadd_tb/floatadd_test/equalcheck
+add wave -position end  sim:/floatadd_tb/floatadd_test/addm
+add wave -position end  sim:/floatadd_tb/floatadd_test/normal
+add wave -position end  sim:/floatadd_tb/floatadd_test/over
+add wave -position end  sim:/floatadd_tb/floatadd_test/clk
+add wave -position end  sim:/floatadd_tb/floatadd_test/rst
+add wave -position end  sim:/floatadd_tb/floatadd_test/x
+add wave -position end  sim:/floatadd_tb/floatadd_test/y
+add wave -position end  sim:/floatadd_tb/floatadd_test/z
+add wave -position end  sim:/floatadd_tb/floatadd_test/overflow
+add wave -position end  sim:/floatadd_tb/floatadd_test/m_x
+add wave -position end  sim:/floatadd_tb/floatadd_test/m_y
+add wave -position end  sim:/floatadd_tb/floatadd_test/m_z
+add wave -position end  sim:/floatadd_tb/floatadd_test/exponent_x
+add wave -position end  sim:/floatadd_tb/floatadd_test/exponent_y
+add wave -position end  sim:/floatadd_tb/floatadd_test/exponent_z
+add wave -position end  sim:/floatadd_tb/floatadd_test/state_now
+add wave -position end  sim:/floatadd_tb/floatadd_test/state_next
+add wave -position end  sim:/floatadd_tb/floatadd_test/sign_z
+add wave -position end  sim:/floatadd_tb/floatadd_test/sign_x
+add wave -position end  sim:/floatadd_tb/floatadd_test/sign_y
+add wave -position end  sim:/floatadd_tb/floatadd_test/out_x
+add wave -position end  sim:/floatadd_tb/floatadd_test/out_y
+add wave -position end  sim:/floatadd_tb/floatadd_test/mid_y
+add wave -position end  sim:/floatadd_tb/floatadd_test/mid_x
+add wave -position end  sim:/floatadd_tb/floatadd_test/move_tot
+add wave -position end  sim:/floatadd_tb/floatadd_test/bigger
+# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
+#           File in use by: xl6u21  Hostname: SRV02039  ProcessID: 21544
+#           Attempting to use alternate WLF file "./wlft9bkcwm".
+# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
+#           Using alternate file: ./wlft9bkcwm
+run -all
+# ** Note: $stop    : H:/Msc project/floating point 32 adder/fpadder_tb.sv(111)
+#    Time: 26040 ns  Iteration: 0  Instance: /floatadd_tb
+# Break in Module floatadd_tb at H:/Msc project/floating point 32 adder/fpadder_tb.sv line 111
+# End time: 22:37:52 on Sep 03,2022, Elapsed time: 6:21:23
+# Errors: 1, Warnings: 7