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Commit 8a5ba504 authored by dam1n19's avatar dam1n19
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Renamed Variable

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resources/fpga/package_component.tcl
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...@@ -22,7 +22,7 @@ set component_lib $env(FPGA_COMPONENT_LIB) ...@@ -22,7 +22,7 @@ set component_lib $env(FPGA_COMPONENT_LIB)
source $env(FPGA_COMPONENT_FILELIST) source $env(FPGA_COMPONENT_FILELIST)
# Set Top-level # Set Top-level
set_property top $env(FPGA_DESIGN_TOP) [current_fileset] set_property top $env(FPGA_COMPONENT_TOP) [current_fileset]
# #
# STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design # STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design
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