diff --git a/resources/fpga/package_component.tcl b/resources/fpga/package_component.tcl
index b1098555b1b68197129f39a87838a92b8879d3b8..feaccae4a343481f8ec878696afcbc1a942cdbac 100644
--- a/resources/fpga/package_component.tcl
+++ b/resources/fpga/package_component.tcl
@@ -22,7 +22,7 @@ set component_lib $env(FPGA_COMPONENT_LIB)
 source $env(FPGA_COMPONENT_FILELIST)
 
 # Set Top-level
-set_property top $env(FPGA_DESIGN_TOP) [current_fileset]
+set_property top $env(FPGA_COMPONENT_TOP) [current_fileset]
 
 #
 # STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design