controller/verilog/socdebug_usrt_control.v

@@ -449,7 +449,7 @@ assign  write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
       rx_buf_full     <= nxt_rx_buf_full;
   end
 
-  assign RX_READY_o = !rx_buf_full;
+  assign RX_READY_o = reg_ctrl[1] & !rx_buf_full;
 
   // Registering receive data buffer
   always @(posedge PCLK or negedge PRESETn)