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SoCLabs
SoCDebug Tech
Commits
Commits · ec5a60835a6ed8b44c084f701411914eeda75a4e
ec5a60835a6ed8b44c084f701411914eeda75a4e
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ec5a60835a6ed8b44c084f701411914eeda75a4e
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2
main
default
protected
feat_extio
3 results
socdebug_tech
controller
verilog
socdebug_ahb.v
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authors
dam1n19
dam1n19
dwf1m12
dwf1m12
dwn1c21
dwn1c21
eb3u21
eb3u21
hhp1n22
hhp1n22
John Darlington
JohnD
6 authors
Browse files
Jun 22, 2023
Fixed io stream instantiation wiring and changed clock dividing to a parameter
· ec5a6083
dam1n19
authored
2 years ago
ec5a6083
Jun 03, 2023
Changed default parameter values and fixed column alignment
· 6a6da3cf
dam1n19
authored
2 years ago
6a6da3cf
Restructured Debug Controller
· 5a418341
David Mapstone
authored
2 years ago
5a418341
Update Name to SoCDebug
· 33fb0d88
David Mapstone
authored
2 years ago
33fb0d88
Jun 02, 2023
Started Moving IP into Repo
· db6019d6
dam1n19
authored
2 years ago
db6019d6
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