Changed default parameter values and fixed column alignment

controller/verilog/socdebug_ahb.v

@@ -12,7 +12,7 @@
 module socdebug_ahb #(
     parameter         PROMPT_CHAR   = "]",
     parameter integer FT1248_WIDTH	= 1, // FTDI Interface 1,2,4 width supported
-    parameter integer FT1248_CLKON	= 0  // FTDI clock always on - else quiet when no access
+    parameter integer FT1248_CLKON	= 1  // FTDI clock always on - else quiet when no access
 )(  
     // AHB-lite Master Interface - ADP
     input  wire                     HCLK,
@@ -55,8 +55,8 @@ module socdebug_ahb #(
     input  wire               [7:0] FT_CLKDIV,   // divider prescaler to ensure SCLK <1MHz
     
     // GPIO interface
-    output wire              [7:0] GPO8_o,
-    input  wire              [7:0] GPI8_i
+    output wire               [7:0] GPO8_o,
+    input  wire               [7:0] GPI8_i
 );
 
     // FT1248 to ADP Bus