From 6a6da3cfd4851abf6623991de6389f54593a9854 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Sat, 3 Jun 2023 22:05:49 +0100
Subject: [PATCH] Changed default parameter values and fixed column alignment
---
controller/verilog/socdebug_ahb.v | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/controller/verilog/socdebug_ahb.v b/controller/verilog/socdebug_ahb.v
index b361c5e..32b880d 100644
--- a/controller/verilog/socdebug_ahb.v
+++ b/controller/verilog/socdebug_ahb.v
@@ -12,7 +12,7 @@
module socdebug_ahb #(
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 0 // FTDI clock always on - else quiet when no access
+ parameter integer FT1248_CLKON = 1 // FTDI clock always on - else quiet when no access
)(
// AHB-lite Master Interface - ADP
input wire HCLK,
@@ -55,8 +55,8 @@ module socdebug_ahb #(
input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
- output wire [7:0] GPO8_o,
- input wire [7:0] GPI8_i
+ output wire [7:0] GPO8_o,
+ input wire [7:0] GPI8_i
);
// FT1248 to ADP Bus
--
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