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SoCLabs
SoCDebug Tech
Commits
049294a8aa4385e4b2e2a03210b315a574e2a787
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2
main
default
protected
feat_extio
2 results
socdebug_tech
socket
vivado_packages
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authors
dam1n19
dam1n19
dwf1m12
dwf1m12
dwn1c21
dwn1c21
eb3u21
eb3u21
hhp1n22
hhp1n22
John Darlington
JohnD
6 authors
Nov 05, 2024
update xilinx lifecycle to Production (was Pre-Production)
· 049294a8
dwf1m12
authored
4 months ago
049294a8
Oct 08, 2024
support FPGA targets other than zynqplus
· 05574880
dwf1m12
authored
5 months ago
05574880
Oct 02, 2024
refactor socdebug for extio8x4 integration
· 05781fa3
dwf1m12
authored
5 months ago
05781fa3
Jul 04, 2023
Added UART Packaging
· 27140834
dam1n19
authored
1 year ago
27140834
Updated make recipies and removed unused ft1248 axi stream package
· 6afabad6
dam1n19
authored
1 year ago
6afabad6
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