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SoCLabs
SoCDebug Tech
Commits
e7702694
Commit
e7702694
authored
10 months ago
by
dwf1m12
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add TX/RX enable to usrt stream channels, and re-factor for EXTIO support
parent
7572912a
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controller/verilog/socdebug_ahb.v
+30
-128
30 additions, 128 deletions
controller/verilog/socdebug_ahb.v
controller/verilog/socdebug_usrt_control.v
+14
-14
14 additions, 14 deletions
controller/verilog/socdebug_usrt_control.v
with
44 additions
and
142 deletions
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