diff --git a/controller/verilog/socdebug_ahb.v b/controller/verilog/socdebug_ahb.v
index cb071deac27c52660a0125bf6beb36d5906a5fd4..9676a36789bbf944c643600a21cc93a04aff2b89 100644
--- a/controller/verilog/socdebug_ahb.v
+++ b/controller/verilog/socdebug_ahb.v
@@ -10,10 +10,7 @@
//-----------------------------------------------------------------------------
module socdebug_ahb #(
- parameter PROMPT_CHAR = "]",
- parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
- parameter [7:0] FT1248_CLKDIV = 8'd03 // Clock Division Ratio
+ parameter PROMPT_CHAR = "]"
)(
// AHB-lite Master Interface - ADP
input wire HCLK,
@@ -30,124 +27,29 @@ module socdebug_ahb #(
input wire HREADY_i,
input wire HRESP_i,
- // APB Slave Interface - USRT
- input wire PCLK, // Clock
- input wire PCLKG, // Gated Clock
- input wire PRESETn, // Reset
-
- input wire PSEL_i, // Device select
- input wire [11:2] PADDR_i, // Address
- input wire PENABLE_i, // Transfer control
- input wire PWRITE_i, // Write control
- input wire [31:0] PWDATA_i, // Write data
-
- output wire [31:0] PRDATA_o, // Read data
- output wire PREADY_o, // Device ready
- output wire PSLVERR_o, // Device error response
+ // USRT0 TXD axi byte stream
+ output wire ADP_RXD_TVALID_o,
+ output wire [ 7:0] ADP_RXD_TDATA_o ,
+ input wire ADP_RXD_TREADY_i,
+ // USRT0 RXD axi byte stream
+ input wire ADP_TXD_TVALID_i,
+ input wire [ 7:0] ADP_TXD_TDATA_i ,
+ output wire ADP_TXD_TREADY_o,
- // FT1248 Interace - FT1248
- output wire FT_CLK_O, // SCLK
- output wire FT_SSN_O, // SS_N
- input wire FT_MISO_I, // MISO
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
- output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
- input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
+ // USRT0 TXD axi byte stream
+ output wire STD_RXD_TVALID_o,
+ output wire [ 7:0] STD_RXD_TDATA_o ,
+ input wire STD_RXD_TREADY_i,
+ // USRT0 RXD axi byte stream
+ input wire STD_TXD_TVALID_i,
+ input wire [ 7:0] STD_TXD_TDATA_i ,
+ output wire STD_TXD_TREADY_o,
// GPIO interface
output wire [7:0] GPO8_o,
input wire [7:0] GPI8_i
);
- // FT1248 to ADP Bus
- wire FT1248_ADP_TVALID;
- wire [ 7:0] FT1248_ADP_TDATA;
- wire FT1248_ADP_TREADY;
-
- // ADP to FT1248 Bus
- wire ADP_FT1248_TVALID;
- wire [ 7:0] ADP_FT1248_TDATA;
- wire ADP_FT1248_TREADY;
-
- // USRT to ADP Bus
- wire USRT_ADP_TVALID;
- wire [ 7:0] USRT_ADP_TDATA;
- wire USRT_ADP_TREADY;
-
- // ADP to USRT Bus
- wire ADP_USRT_TVALID;
- wire [ 7:0] ADP_USRT_TDATA;
- wire ADP_USRT_TREADY;
-
- // Clock Divsion Ratio
- wire [7:0] FT_CLKDIV;
- assign FT_CLKDIV = FT1248_CLKDIV;
-
- // Instantiation of USRT Controller
- socdebug_usrt_control u_usrt_control (
- // APB Clock and Reset Signals
- .PCLK (PCLK),
- .PCLKG (PCLKG), // Gated PCLK for bus
- .PRESETn (PRESETn),
-
- // APB Interface Signals
- .PSEL (PSEL_i),
- .PADDR (PADDR_i),
- .PENABLE (PENABLE_i),
- .PWRITE (PWRITE_i),
- .PWDATA (PWDATA_i),
- .PRDATA (PRDATA_o),
- .PREADY (PREADY_o),
- .PSLVERR (PSLVERR_o),
-
- .ECOREVNUM (4'h0),
-
- // ADP Interface - From USRT to ADP
- .TX_VALID_o (USRT_ADP_TVALID),
- .TX_DATA8_o (USRT_ADP_TDATA),
- .TX_READY_i (USRT_ADP_TREADY),
-
- // ADP Interface - From ADP to USRT
- .RX_VALID_i (ADP_USRT_TVALID),
- .RX_DATA8_i (ADP_USRT_TDATA),
- .RX_READY_o (ADP_USRT_TREADY),
-
- // Interrupt Interfaces
- .TXINT ( ), // Transmit Interrupt
- .RXINT ( ), // Receive Interrupt
- .TXOVRINT ( ), // Transmit Overrun Interrupt
- .RXOVRINT ( ), // Receive Overrun Interrupt
- .UARTINT ( ) // Combined Interrupt
- );
-
- // Instantiation of FT1248 Controller
- socdebug_ft1248_control #(
- .FT1248_WIDTH (FT1248_WIDTH),
- .FT1248_CLKON (FT1248_CLKON)
- ) u_ft1248_control (
- .clk (HCLK),
- .resetn (HRESETn),
- .ft_clkdiv (FT_CLKDIV),
- .ft_clk_o (FT_CLK_O),
- .ft_ssn_o (FT_SSN_O),
- .ft_miso_i (FT_MISO_I),
- .ft_miosio_o (FT_MIOSIO_O),
- .ft_miosio_e (FT_MIOSIO_E),
- .ft_miosio_z (FT_MIOSIO_Z),
- .ft_miosio_i (FT_MIOSIO_I),
-
- // ADP Interface - FT1248 to ADP
- .txd_tvalid (FT1248_ADP_TVALID),
- .txd_tdata (FT1248_ADP_TDATA),
- .txd_tready (FT1248_ADP_TREADY),
- .txd_tlast ( ),
-
- // ADP Interface - ADP to FT1248
- .rxd_tvalid (ADP_FT1248_TVALID),
- .rxd_tdata (ADP_FT1248_TDATA),
- .rxd_tready (ADP_FT1248_TREADY),
- .rxd_tlast (1'b0)
- );
// Instantiation of ADP AHB Controller
socdebug_adp_control #(
@@ -173,25 +75,25 @@ module socdebug_ahb #(
.GPI8_i (GPI8_i),
// USRT Interface - From ADP to USRT
- .STDTX_TVALID_o (ADP_USRT_TVALID),
- .STDTX_TDATA_o (ADP_USRT_TDATA),
- .STDTX_TREADY_i (ADP_USRT_TREADY),
+ .STDTX_TVALID_o (STD_RXD_TVALID_o),
+ .STDTX_TDATA_o (STD_RXD_TDATA_o ),
+ .STDTX_TREADY_i (STD_RXD_TREADY_i),
// USRT Interface - From USRT to ADP
- .STDRX_TVALID_i (USRT_ADP_TVALID),
- .STDRX_TDATA_i (USRT_ADP_TDATA),
- .STDRX_TREADY_o (USRT_ADP_TREADY),
+ .STDRX_TVALID_i (STD_TXD_TVALID_i),
+ .STDRX_TDATA_i (STD_TXD_TDATA_i ),
+ .STDRX_TREADY_o (STD_TXD_TREADY_o),
// FT1248 Interface - From FT1248 to ADP
- .COMRX_TVALID_i (FT1248_ADP_TVALID),
- .COMRX_TDATA_i (FT1248_ADP_TDATA),
- .COMRX_TREADY_o (FT1248_ADP_TREADY),
+ .COMRX_TVALID_i (ADP_TXD_TVALID_i),
+ .COMRX_TDATA_i (ADP_TXD_TDATA_i ),
+ .COMRX_TREADY_o (ADP_TXD_TREADY_o),
// FT1248 Interface - From ADP to FT1248
- .COMTX_TVALID_o (ADP_FT1248_TVALID),
- .COMTX_TDATA_o (ADP_FT1248_TDATA),
- .COMTX_TREADY_i (ADP_FT1248_TREADY)
+ .COMTX_TVALID_o (ADP_RXD_TVALID_o),
+ .COMTX_TDATA_o (ADP_RXD_TDATA_o ),
+ .COMTX_TREADY_i (ADP_RXD_TREADY_i)
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/controller/verilog/socdebug_usrt_control.v b/controller/verilog/socdebug_usrt_control.v
index 7222fbd5e53c54c49c71aaf66bbedf184d3d8aa2..e65041d581d60f79f648c5c1b4b555fc1f1b5571 100644
--- a/controller/verilog/socdebug_usrt_control.v
+++ b/controller/verilog/socdebug_usrt_control.v
@@ -39,24 +39,24 @@
// 0x00 R RXD[7:0] Received Data
// W TXD[7:0] Transmit data
// 0x04 RW STAT[3:0]
-// [3] RX buffer overrun (write 1 to clear)
-// [2] TX buffer overrun (write 1 to clear)
+// [3] RX buffer overrun (write 1 to clear) // 0 for USRT
+// [2] TX buffer overrun (write 1 to clear) // 0 for USRT
// [1] RX buffer full (Read only)
// [0] TX buffer full (Read only)
// 0x08 RW CTRL[3:0] TxIntEn, RxIntEn, TxEn, RxEn
// [6] High speed test mode Enable
-// [5] RX overrun interrupt enable
-// [4] TX overrun interrupt enable
+// [5] RX overrun interrupt enable // N/A for USRT
+// [4] TX overrun interrupt enable // N/A for USRT
// [3] RX Interrupt Enable
// [2] TX Interrupt Enable
// [1] RX Enable
// [0] TX Enable
// 0x0C R/Wc intr_status/INTCLEAR
-// [3] RX overrun interrupt
-// [2] TX overrun interrupt
+// [3] RX overrun interrupt // 0 for USRT
+// [2] TX overrun interrupt // 0 for USRT
// [1] RX interrupt
// [0] TX interrupt
-// 0x10 RW BAUDDIV[19:0] Baud divider
+// 0x10 RW BAUDDIV[19:0] Baud divider // Not Used for USRT
// (minimum value is 16)
// 0x3E0 - 0x3FC ID registers
//-------------------------------------
@@ -101,13 +101,13 @@ localparam ARM_CMSDK_APB_UART_PID5 = 8'h00;
localparam ARM_CMSDK_APB_UART_PID6 = 8'h00;
localparam ARM_CMSDK_APB_UART_PID7 = 8'h00;
localparam ARM_CMSDK_APB_UART_PID0 = 8'h21;
-localparam ARM_CMSDK_APB_UART_PID1 = 8'hB8;
-localparam ARM_CMSDK_APB_UART_PID2 = 8'h1B;
+localparam ARM_CMSDK_APB_UART_PID1 = 8'hb8;
+localparam ARM_CMSDK_APB_UART_PID2 = 8'h1b;
localparam ARM_CMSDK_APB_UART_PID3 = 4'h0;
-localparam ARM_CMSDK_APB_UART_CID0 = 8'h0D;
-localparam ARM_CMSDK_APB_UART_CID1 = 8'hF0;
+localparam ARM_CMSDK_APB_UART_CID0 = 8'h0d;
+localparam ARM_CMSDK_APB_UART_CID1 = 8'hf0;
localparam ARM_CMSDK_APB_UART_CID2 = 8'h05;
-localparam ARM_CMSDK_APB_UART_CID3 = 8'hB1;
+localparam ARM_CMSDK_APB_UART_CID3 = 8'hb1;
// original external IOs
wire RXD = 1'b1; // Serial input
@@ -411,7 +411,7 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
begin
if (~PRESETn)
tx_buf_full <= 1'b0;
- else if (write_enable00) // | tx_buf_clear)
+ else if (write_enable00 & reg_ctrl[0]) // | tx_buf_clear)
tx_buf_full <= write_enable00;
else if (tx_buf_full & TX_READY_i) // AXI stream ack
tx_buf_full <= 0;
@@ -619,7 +619,7 @@ assign RX_READY_o = !rx_buf_full;
begin
if (~PRESETn)
rx_buf_full <= 1'b0;
- else if (rxbuf_sample | rx_data_read)
+ else if ( & reg_ctrl[1] & (rxbuf_sample | rx_data_read))
rx_buf_full <= nxt_rx_buf_full;
end