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Commit ad581b67 authored by dwf1m12's avatar dwf1m12
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clean up the 'USRT' streamio module

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controller/verilog/socdebug_usrt_control.v
+ 10
− 198
View file @ ad581b67
...@@ -315,8 +315,6 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004); ...@@ -315,8 +315,6 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
end end
end end
// Register read data // Register read data
always @(posedge PCLKG or negedge PRESETn) always @(posedge PCLKG or negedge PRESETn)
begin begin
...@@ -419,159 +417,21 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004); ...@@ -419,159 +417,21 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
assign TX_VALID_o = tx_buf_full; assign TX_VALID_o = tx_buf_full;
// Increment TickCounter
assign nxt_tx_tick_cnt = ((tx_state==4'h1) & reg_baud_tick) ? {5{1'b0}} :
tx_tick_cnt + {{3{1'b0}},reg_baud_tick};
// Registering TickCounter
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
tx_tick_cnt <= {4{1'b0}};
else if (reg_baud_tick)
tx_tick_cnt <= nxt_tx_tick_cnt[3:0];
end
// Increment state (except Idle(0) and Wait for Tick(1))
assign tx_state_inc = (((&tx_tick_cnt)|(tx_state==4'h1)) & reg_baud_tick)|reg_ctrl[6];
// state increment every cycle of high speed test mode is enabled
// Clear buffer full status when data is load into shift register
assign tx_buf_clear = ((tx_state==4'h0) & tx_buf_full) |
((tx_state==4'hB) & tx_buf_full & tx_state_inc);
// tx_state machine
// 0 = Idle, 1 = Wait for Tick,
// 2 = Start bit, 3 = D0 .... 10 = D7
// 11 = Stop bit
always @(tx_state or tx_buf_full or tx_state_inc or reg_ctrl)
begin
case (tx_state)
0: begin
nxt_tx_state = (tx_buf_full & reg_ctrl[0]) ? 5'h01 : 5'h00; // New data is written to buffer
end
1, // State 1 : Wait for next Tick
2,3,4,5,6,7,8,9,10: begin // State 2-10: Start bit, D0 - D7
nxt_tx_state = tx_state + {3'b000,tx_state_inc};
end
11: begin // Stop bit , goto next start bit or Idle
nxt_tx_state = (tx_state_inc) ? ( tx_buf_full ? 5'h02:5'h00) : {1'b0, tx_state};
end
default:
nxt_tx_state = {5{1'bx}};
endcase
end
assign tx_state_update = tx_state_inc | ((tx_state==4'h0) & tx_buf_full & reg_ctrl[0]) | (tx_state>4'd11);
// Registering outputs
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
tx_state <= {4{1'b0}};
else if (tx_state_update)
tx_state <= nxt_tx_state[3:0];
end
// Load/shift TX register
assign tx_buf_ctrl_load = (((tx_state==4'h0) & tx_buf_full) |
((tx_state==4'hB) & tx_buf_full & tx_state_inc));
assign tx_buf_ctrl_shift = ((tx_state>4'h2) & tx_state_inc);
assign nxt_tx_shift_buf = tx_buf_ctrl_load ? reg_tx_buf[7:0] : {1'b1,tx_shift_buf[7:1]};
// Registering TX shift register
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
tx_shift_buf <= {8{1'b0}};
else if (tx_buf_ctrl_shift | tx_buf_ctrl_load)
tx_shift_buf <= nxt_tx_shift_buf;
end
// Data output
assign nxt_txd = (tx_state==4'h2) ? 1'b0 :
(tx_state>4'h2) ? tx_shift_buf[0] : 1'b1;
assign update_reg_txd = (nxt_txd != reg_txd);
// Registering outputs
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
reg_txd <= 1'b1;
else if (update_reg_txd)
reg_txd <= nxt_txd;
end
// Generate TX overrun error status // Generate TX overrun error status
assign tx_overrun = tx_buf_full & (~tx_buf_clear) & write_enable00; /// assign tx_overrun = tx_buf_full & (~tx_buf_clear) & write_enable00;
assign tx_overrun = tx_buf_full & write_enable00;
// Connect to external // Connect to external
assign TXD = reg_txd; assign TXD = reg_txd;
assign TXEN = reg_ctrl[0]; assign TXEN = reg_ctrl[0];
// --------------------------------------------
// Receive synchronizer and low pass filter
// Doubling Flip-flop synxt_rx_tick_cntnchroniser
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
begin
rxd_sync_1 <= 1'b1;
rxd_sync_2 <= 1'b1;
end
else if (reg_ctrl[1]) // Turn off synchronizer if receive is not enabled
begin
rxd_sync_1 <= RXD;
rxd_sync_2 <= rxd_sync_1;
end
end
// Averaging low pass filter
assign nxt_rxd_lpf = {rxd_lpf[1:0], rxd_sync_2};
// Registering stage for low pass filter
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
rxd_lpf <= 3'b111;
else if (reg_baud_tick)
rxd_lpf <= nxt_rxd_lpf;
end
// Averaging values
assign rx_shift_in = (rxd_lpf[1] & rxd_lpf[0]) |
(rxd_lpf[1] & rxd_lpf[2]) |
(rxd_lpf[0] & rxd_lpf[2]);
// -------------------------------------------- // --------------------------------------------
// Receive // Receive
assign RX_READY_o = !rx_buf_full;
// Increment TickCounter
assign nxt_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) ? 5'h08 :
rx_tick_cnt + {{3{1'b0}},reg_baud_tick};
assign update_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) | reg_baud_tick;
// Registering other register
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
rx_tick_cnt <= {4{1'b0}};
else if (update_rx_tick_cnt)
rx_tick_cnt <= nxt_rx_tick_cnt[3:0];
end
// Increment state
assign rx_state_inc = ((&rx_tick_cnt) & reg_baud_tick);
// Buffer full status
assign nxt_rx_buf_full = rxbuf_sample | (rx_buf_full & (~rx_data_read)); assign nxt_rx_buf_full = rxbuf_sample | (rx_buf_full & (~rx_data_read));
// Sample shift register when D7 is sampled
/// assign rxbuf_sample = ((rx_state==4'h9) & rx_state_inc);
assign rxbuf_sample = RX_VALID_i & !rx_buf_full; assign rxbuf_sample = RX_VALID_i & !rx_buf_full;
// Reading receive buffer (Set at 1st cycle of APB transfer // Reading receive buffer (Set at 1st cycle of APB transfer
...@@ -580,81 +440,33 @@ assign RX_READY_o = !rx_buf_full; ...@@ -580,81 +440,33 @@ assign RX_READY_o = !rx_buf_full;
// Generate RX overrun error status // Generate RX overrun error status
assign rx_overrun = rx_buf_full & rxbuf_sample & (~rx_data_read); assign rx_overrun = rx_buf_full & rxbuf_sample & (~rx_data_read);
// rx_state machine
// 0 = Idle, 1 = Start of Start bit detected
// 2 = Sample Start bit, 3 = D0 .... 10 = D7
// 11 = Stop bit
// 11, 12, 13, 14, 15: illegal/unused states
always @(rx_state or rx_shift_in or rx_state_inc or reg_ctrl)
begin
case (rx_state)
0: begin
nxt_rx_state = ((~rx_shift_in) & reg_ctrl[1]) ? 5'h01 : 5'h00; // Wait for Start bit
end
1, // State 1 : Wait for middle of start bit
2,3,4,5,6,7,8,9: begin // State 2-9: D0 - D7
nxt_rx_state = rx_state + {3'b000,rx_state_inc};
end
10: begin // Stop bit , goto back to Idle
nxt_rx_state = (rx_state_inc) ? 5'h00 : 5'h0A;
end
default:
nxt_rx_state = {5{1'bx}};
endcase
end
assign rx_state_update = rx_state_inc | ((~rx_shift_in) & reg_ctrl[1]);
// Registering rx_state
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
rx_state <= {4{1'b0}};
else if (rx_state_update)
rx_state <= nxt_rx_state[3:0];
end
// Buffer full status // Buffer full status
always @(posedge PCLK or negedge PRESETn) always @(posedge PCLK or negedge PRESETn)
begin begin
if (~PRESETn) if (~PRESETn)
rx_buf_full <= 1'b0; rx_buf_full <= 1'b0;
else if ( & reg_ctrl[1] & (rxbuf_sample | rx_data_read)) else if ( reg_ctrl[1] & (rxbuf_sample | rx_data_read))
rx_buf_full <= nxt_rx_buf_full; rx_buf_full <= nxt_rx_buf_full;
end end
// Sample receive buffer assign RX_READY_o = !rx_buf_full;
/// assign nxt_rx_buf = {rx_shift_in, rx_shift_buf};
assign nxt_rx_buf = RX_DATA8_i[7:0];
// Registering receive data buffer // Registering receive data buffer
always @(posedge PCLK or negedge PRESETn) always @(posedge PCLK or negedge PRESETn)
begin begin
if (~PRESETn) if (~PRESETn)
reg_rx_buf <= {8{1'b0}}; reg_rx_buf <= {8{1'b0}};
else if (rxbuf_sample) else if (rxbuf_sample)
reg_rx_buf <= nxt_rx_buf; reg_rx_buf <= RX_DATA8_i[7:0];
end end
// Shift register
assign nxt_rx_shift_buf= {rx_shift_in, rx_shift_buf[6:1]};
// Registering shift buffer
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
rx_shift_buf <= {7{1'b0}};
else if (rx_state_inc)
rx_shift_buf <= nxt_rx_shift_buf;
end
// -------------------------------------------- // --------------------------------------------
// Interrupts // Interrupts
// Set by event // Set by event
assign intr_stat_set[1] = reg_ctrl[3] & rxbuf_sample; // A new receive data is sampled /// assign intr_stat_set[1] = reg_ctrl[3] & rxbuf_sample; // A new receive data is sampled
assign intr_stat_set[0] = reg_ctrl[2] & reg_ctrl[0] & tx_buf_full & tx_buf_clear; assign intr_stat_set[1] = reg_ctrl[3] & reg_ctrl[1] & rxbuf_sample; // A new receive data is sampled
// Falling edge of buffer full /// assign intr_stat_set[0] = reg_ctrl[2] & reg_ctrl[0] & tx_buf_full; // & tx_buf_clear;
assign intr_stat_set[0] = reg_ctrl[2] & reg_ctrl[0] & tx_buf_full & TX_READY_i; // Falling edge of buffer full
// Clear by write to IntClear register // Clear by write to IntClear register
assign intr_stat_clear[1:0] = {2{write_enable0c}} & PWDATA[1:0]; assign intr_stat_clear[1:0] = {2{write_enable0c}} & PWDATA[1:0];
......
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