Modified git submodules location

.gitmodules

+[submodule "socket/uart_axi_master/core_dbg_bridge"]
+	path = socket/uart_axi_master/core_dbg_bridge
+	url = https://github.com/ultraembedded/core_dbg_bridge.git

flist/uart_axi_master_ip.flist

@@ -12,7 +12,7 @@
 // Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
 //-----------------------------------------------------------------------------
 
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
\ No newline at end of file
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge_fifo.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge_uart.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/wrapper/verilog/uart_axi_master.v
\ No newline at end of file

core_dbg_bridge @ 3ea8f99c

+Subproject commit 3ea8f99cb458acf3f6cfe27862afe77d560caf08