diff --git a/.gitmodules b/.gitmodules
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ef48a8de72cae920125ab46851c19f2aaab32b6c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "socket/uart_axi_master/core_dbg_bridge"]
+	path = socket/uart_axi_master/core_dbg_bridge
+	url = https://github.com/ultraembedded/core_dbg_bridge.git
diff --git a/flist/uart_axi_master_ip.flist b/flist/uart_axi_master_ip.flist
index 36e5e360ca877b5531aa937571cc80d10f0ff458..a4477d2dd545917a7045a3afc63d2ee26737ecb6 100644
--- a/flist/uart_axi_master_ip.flist
+++ b/flist/uart_axi_master_ip.flist
@@ -12,7 +12,7 @@
 // Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
 //-----------------------------------------------------------------------------
 
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
\ No newline at end of file
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge_fifo.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge_uart.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/core_dbg_bridge/src_v/dbg_bridge.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/wrapper/verilog/uart_axi_master.v
\ No newline at end of file
diff --git a/socket/uart_axi_master/core_dbg_bridge b/socket/uart_axi_master/core_dbg_bridge
new file mode 160000
index 0000000000000000000000000000000000000000..3ea8f99cb458acf3f6cfe27862afe77d560caf08
--- /dev/null
+++ b/socket/uart_axi_master/core_dbg_bridge
@@ -0,0 +1 @@
+Subproject commit 3ea8f99cb458acf3f6cfe27862afe77d560caf08