update the FPGA IP components for extio controller

fpga/makefile

@@ -20,6 +20,11 @@ package_adp_control:
 	@mkdir -p $(IMP_SOCKET_DIR)
 	@cp -r $(RTL_SOCKET_DIR)/ADPcontrol_1.0 $(IMP_SOCKET_DIR)/ADPcontrol_1.0
 
+package_extio_control:
+	@echo Packaging Uart To AXI Master
+	@mkdir -p $(IMP_SOCKET_DIR)
+	@cp -r $(RTL_SOCKET_DIR)/extio8x4_axis_target_1.0 $(IMP_SOCKET_DIR)/extio8x4_axis_target_1.0
+	
 package_axi_stream_io:
 	@echo Packaging Uart To AXI Master
 	@mkdir -p $(IMP_SOCKET_DIR)
@@ -35,7 +40,7 @@ package_uart_to_axi:
 	@mkdir -p $(IMP_SOCKET_DIR)
 	@cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(IMP_SOCKET_DIR)/uart_to_AXI_master_1.0
 
-package_socket: clean_socket package_uart package_ft1248_to_stream package_axi_stream_io package_adp_control
+package_socket: clean_socket package_uart package_ft1248_to_stream package_axi_stream_io package_adp_control package_extio_control
 # package_socket: clean_socket package_uart package_f232h package_streamio package_adp_control
 
 clean_socket: