From 3a7164e0b8e1f1fa0387aea9e9003d2e4ebf1047 Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Fri, 4 Oct 2024 14:59:32 +0100 Subject: [PATCH] update the FPGA IP components for extio controller --- fpga/makefile | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/fpga/makefile b/fpga/makefile index fda0d10..3fad442 100644 --- a/fpga/makefile +++ b/fpga/makefile @@ -19,6 +19,11 @@ package_adp_control: @echo Packaging Uart To AXI Master @mkdir -p $(IMP_SOCKET_DIR) @cp -r $(RTL_SOCKET_DIR)/ADPcontrol_1.0 $(IMP_SOCKET_DIR)/ADPcontrol_1.0 + +package_extio_control: + @echo Packaging Uart To AXI Master + @mkdir -p $(IMP_SOCKET_DIR) + @cp -r $(RTL_SOCKET_DIR)/extio8x4_axis_target_1.0 $(IMP_SOCKET_DIR)/extio8x4_axis_target_1.0 package_axi_stream_io: @echo Packaging Uart To AXI Master @@ -35,7 +40,7 @@ package_uart_to_axi: @mkdir -p $(IMP_SOCKET_DIR) @cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(IMP_SOCKET_DIR)/uart_to_AXI_master_1.0 -package_socket: clean_socket package_uart package_ft1248_to_stream package_axi_stream_io package_adp_control +package_socket: clean_socket package_uart package_ft1248_to_stream package_axi_stream_io package_adp_control package_extio_control # package_socket: clean_socket package_uart package_f232h package_streamio package_adp_control clean_socket: @@ -176,4 +181,4 @@ package_adp_manager: flist_adp_manager @cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl @mkdir -p $(ADP_MANAGER_IMP_DIR)/logs @cp $(RUN_DIR)/vivado.log $(ADP_MANAGER_IMP_DIR)/logs - @echo AXI Stream Interface Packaged \ No newline at end of file + @echo AXI Stream Interface Packaged -- GitLab