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Commit 04639f9c authored by dam1n19's avatar dam1n19
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Updated copy_to directory for fpga flow

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fpga/makefile
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...@@ -64,7 +64,7 @@ UART_CORE_REV ?= 1 ...@@ -64,7 +64,7 @@ UART_CORE_REV ?= 1
flist_uart: flist_uart:
@mkdir -p $(UART_TCL_FLIST_DIR) @mkdir -p $(UART_TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \ @(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR);) $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR)/src;)
# Environment Variables for Packaging UART to AXI Master # Environment Variables for Packaging UART to AXI Master
package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST) package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST)
...@@ -96,7 +96,7 @@ F232H_CORE_REV ?= 1 ...@@ -96,7 +96,7 @@ F232H_CORE_REV ?= 1
flist_f232h: flist_f232h:
@mkdir -p $(F232H_TCL_FLIST_DIR) @mkdir -p $(F232H_TCL_FLIST_DIR)
@(cd $(F232H_TCL_FLIST_DIR); \ @(cd $(F232H_TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR);) $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR)/src;)
# Environment Variables for Packaging F232H Emulator # Environment Variables for Packaging F232H Emulator
package_f232h: export FPGA_COMPONENT_FILELIST = $(F232H_TCL_OUTPUT_FILELIST) package_f232h: export FPGA_COMPONENT_FILELIST = $(F232H_TCL_OUTPUT_FILELIST)
...@@ -128,7 +128,7 @@ STREAMIO_CORE_REV ?= 1 ...@@ -128,7 +128,7 @@ STREAMIO_CORE_REV ?= 1
flist_streamio: flist_streamio:
@mkdir -p $(STREAMIO_TCL_FLIST_DIR) @mkdir -p $(STREAMIO_TCL_FLIST_DIR)
@(cd $(STREAMIO_TCL_FLIST_DIR); \ @(cd $(STREAMIO_TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(STREAMIO_FLIST) -o $(STREAMIO_TCL_OUTPUT_FILELIST) -r $(STREAMIO_IMP_DIR);) $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(STREAMIO_FLIST) -o $(STREAMIO_TCL_OUTPUT_FILELIST) -r $(STREAMIO_IMP_DIR)/src;)
# Environment Variables for Packaging NanoSoC # Environment Variables for Packaging NanoSoC
package_streamio: export FPGA_COMPONENT_FILELIST = $(STREAMIO_TCL_OUTPUT_FILELIST) package_streamio: export FPGA_COMPONENT_FILELIST = $(STREAMIO_TCL_OUTPUT_FILELIST)
...@@ -160,7 +160,7 @@ ADP_MANAGER_CORE_REV ?= 1 ...@@ -160,7 +160,7 @@ ADP_MANAGER_CORE_REV ?= 1
flist_adp_manager: flist_adp_manager:
@mkdir -p $(ADP_MANAGER_TCL_FLIST_DIR) @mkdir -p $(ADP_MANAGER_TCL_FLIST_DIR)
@(cd $(ADP_MANAGER_TCL_FLIST_DIR); \ @(cd $(ADP_MANAGER_TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(ADP_MANAGER_FLIST) -o $(ADP_MANAGER_TCL_OUTPUT_FILELIST) -r $(ADP_MANAGER_IMP_DIR);) $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(ADP_MANAGER_FLIST) -o $(ADP_MANAGER_TCL_OUTPUT_FILELIST) -r $(ADP_MANAGER_IMP_DIR)/src;)
# Environment Variables for Packaging NanoSoC # Environment Variables for Packaging NanoSoC
package_adp_manager: export FPGA_COMPONENT_FILELIST = $(ADP_MANAGER_TCL_OUTPUT_FILELIST) package_adp_manager: export FPGA_COMPONENT_FILELIST = $(ADP_MANAGER_TCL_OUTPUT_FILELIST)
......
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