diff --git a/fpga/makefile b/fpga/makefile
index 2e0856b457efd2a6e52215fc50d1641889892003..86c2fb364a513fc452bc726965b285654f1e1840 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -64,7 +64,7 @@ UART_CORE_REV   ?= 1
 flist_uart:
 	@mkdir -p $(UART_TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR)/src;)
 	
 # Environment Variables for Packaging UART to AXI Master
 package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST)
@@ -96,7 +96,7 @@ F232H_CORE_REV             ?= 1
 flist_f232h:
 	@mkdir -p $(F232H_TCL_FLIST_DIR)
 	@(cd $(F232H_TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR)/src;)
 	
 # Environment Variables for Packaging F232H Emulator
 package_f232h: export FPGA_COMPONENT_FILELIST = $(F232H_TCL_OUTPUT_FILELIST)
@@ -128,7 +128,7 @@ STREAMIO_CORE_REV             ?= 1
 flist_streamio:
 	@mkdir -p $(STREAMIO_TCL_FLIST_DIR)
 	@(cd $(STREAMIO_TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(STREAMIO_FLIST) -o $(STREAMIO_TCL_OUTPUT_FILELIST) -r $(STREAMIO_IMP_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(STREAMIO_FLIST) -o $(STREAMIO_TCL_OUTPUT_FILELIST) -r $(STREAMIO_IMP_DIR)/src;)
 	
 # Environment Variables for Packaging NanoSoC
 package_streamio: export FPGA_COMPONENT_FILELIST = $(STREAMIO_TCL_OUTPUT_FILELIST)
@@ -160,7 +160,7 @@ ADP_MANAGER_CORE_REV             ?= 1
 flist_adp_manager:
 	@mkdir -p $(ADP_MANAGER_TCL_FLIST_DIR)
 	@(cd $(ADP_MANAGER_TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(ADP_MANAGER_FLIST) -o $(ADP_MANAGER_TCL_OUTPUT_FILELIST) -r $(ADP_MANAGER_IMP_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(ADP_MANAGER_FLIST) -o $(ADP_MANAGER_TCL_OUTPUT_FILELIST) -r $(ADP_MANAGER_IMP_DIR)/src;)
 	
 # Environment Variables for Packaging NanoSoC
 package_adp_manager: export FPGA_COMPONENT_FILELIST = $(ADP_MANAGER_TCL_OUTPUT_FILELIST)