Started Liniting SLCore by itself

hal/slcorem0_ip.waive

+//-----------------------------------------------------------------------------
+// SLCore M0 Lint Waivers 
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Wavier file for SLCoreM0
+//-----------------------------------------------------------------------------
+
+lint_checking designunit = slcorem0
+{
+    // Clock and Reset Naming drops SYS and CORE prefix in Instantiated Modules
+    DIFCLK {"SYS_|CORE_"} off;
+    DIFRST {"SYS_|CORE_"} off;
+    
+}
+
+lint_checking designunit = slcorem0_integration
+{
+    // Constant Conditional for Debug Configuration
+    CONSTC {"cfg_dbg"} off;
+}
+
+lint_checking designunit = slcorem0_prmu
+{
+    // Constant Conditional for Clock Gating
+    CONSTC {"CLKGATE"} off;
+    
+    // With CLock Gating Disabled, Clocks may be aliased
+    DALIAS {"CLK"} off;
+    DIFCLK {"CLKGATE"} off;
+}

makefile

+#-----------------------------------------------------------------------------
+# SoCLabs SLCore M0 Flow Makefile 
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
+
+LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/slcorem0
+LINT_INFO_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal
+
+# Core Design Filelist
+DESIGN_VC   ?= $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist
+
+# Defines
+DEFINES_VC  += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC 
+
+# Black Box for Lint
+HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/cortexm0_ip.bb
+
+# Lint Waivers
+HAL_WAIVE = -design_info $(LINT_INFO_DIR)/slcorem0_ip.waive
+
+lint_xm:
+	@rm -rf $(LINT_DIR) 
+	@mkdir -p $(LINT_DIR)
+	cd $(LINT_DIR); hal -f $(DESIGN_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top slcorem0 $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
+

src/verilog/slcorem0.v

@@ -232,7 +232,7 @@ module slcorem0 #(
     .NMI           (CORE_NMI),
     .IRQLATENCY    (8'h00),
 
-    .ECOREVNUM     (28'h0),
+    .ECOREVNUM     (28'd0),
     
     // Systick
     .STCLKEN       (CORE_STCLKEN),