From d8d9c80f3bc2307ff8b71d2b32b6b14bb864c7cc Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 23 Jun 2023 11:21:34 +0100
Subject: [PATCH] Started Liniting SLCore by itself
---
hal/slcorem0_ip.waive | 37 +++++++++++++++++++++++++++++++++++++
makefile | 33 +++++++++++++++++++++++++++++++++
src/verilog/slcorem0.v | 2 +-
3 files changed, 71 insertions(+), 1 deletion(-)
create mode 100644 hal/slcorem0_ip.waive
create mode 100644 makefile
diff --git a/hal/slcorem0_ip.waive b/hal/slcorem0_ip.waive
new file mode 100644
index 0000000..9e7d258
--- /dev/null
+++ b/hal/slcorem0_ip.waive
@@ -0,0 +1,37 @@
+//-----------------------------------------------------------------------------
+// SLCore M0 Lint Waivers
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Wavier file for SLCoreM0
+//-----------------------------------------------------------------------------
+
+lint_checking designunit = slcorem0
+{
+ // Clock and Reset Naming drops SYS and CORE prefix in Instantiated Modules
+ DIFCLK {"SYS_|CORE_"} off;
+ DIFRST {"SYS_|CORE_"} off;
+
+}
+
+lint_checking designunit = slcorem0_integration
+{
+ // Constant Conditional for Debug Configuration
+ CONSTC {"cfg_dbg"} off;
+}
+
+lint_checking designunit = slcorem0_prmu
+{
+ // Constant Conditional for Clock Gating
+ CONSTC {"CLKGATE"} off;
+
+ // With CLock Gating Disabled, Clocks may be aliased
+ DALIAS {"CLK"} off;
+ DIFCLK {"CLKGATE"} off;
+}
diff --git a/makefile b/makefile
new file mode 100644
index 0000000..096f4a6
--- /dev/null
+++ b/makefile
@@ -0,0 +1,33 @@
+#-----------------------------------------------------------------------------
+# SoCLabs SLCore M0 Flow Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
+
+LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/slcorem0
+LINT_INFO_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal
+
+# Core Design Filelist
+DESIGN_VC ?= $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist
+
+# Defines
+DEFINES_VC += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC
+
+# Black Box for Lint
+HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/cortexm0_ip.bb
+
+# Lint Waivers
+HAL_WAIVE = -design_info $(LINT_INFO_DIR)/slcorem0_ip.waive
+
+lint_xm:
+ @rm -rf $(LINT_DIR)
+ @mkdir -p $(LINT_DIR)
+ cd $(LINT_DIR); hal -f $(DESIGN_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top slcorem0 $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
+
diff --git a/src/verilog/slcorem0.v b/src/verilog/slcorem0.v
index cf353db..97c4f8f 100644
--- a/src/verilog/slcorem0.v
+++ b/src/verilog/slcorem0.v
@@ -232,7 +232,7 @@ module slcorem0 #(
.NMI (CORE_NMI),
.IRQLATENCY (8'h00),
- .ECOREVNUM (28'h0),
+ .ECOREVNUM (28'd0),
// Systick
.STCLKEN (CORE_STCLKEN),
--
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