Skip to content
Snippets Groups Projects
Commit 8c36b79e authored by dam1n19's avatar dam1n19
Browse files

Broke verification code into own clocked block

parent b7352b6e
No related branches found
No related tags found
No related merge requests found
...@@ -122,11 +122,15 @@ module tb_message_build; ...@@ -122,11 +122,15 @@ module tb_message_build;
logic [511:0] data_out_check; logic [511:0] data_out_check;
logic data_out_last_check; logic data_out_last_check;
logic check_output;
logic test_end;
// Handle Output Ready Driving // Handle Output Ready Driving
always_ff @(posedge clk, negedge nrst) begin: data_out_recieve always_ff @(posedge clk, negedge nrst) begin: data_out_recieve
if (!nrst) begin if (!nrst) begin
data_out_ready <= 1'b0; data_out_ready <= 1'b0;
check_output <= 1'b0;
test_end <= 1'b0;
end else begin end else begin
// Synchronise Ready to Clock // Synchronise Ready to Clock
if (data_out_drive_ready) begin if (data_out_drive_ready) begin
...@@ -136,25 +140,36 @@ module tb_message_build; ...@@ -136,25 +140,36 @@ module tb_message_build;
end end
// Check Data on Handshake // Check Data on Handshake
if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
check_output <= 1'b1;
if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
data_out_check <= data_out_queue.pop_front(); data_out_check <= data_out_queue.pop_front();
assert (data_out == data_out_check) else begin
$error("data_out missmatch! recieve: %x != check: %x", data_out, data_out_check);
$finish;
end
data_out_last_check <= data_out_last_queue.pop_front(); data_out_last_check <= data_out_last_queue.pop_front();
assert (data_out_last == data_out_last_check) else begin
$error("data_out_last missmatch! recieve: %x != check: %x", data_out_last, data_out_last_check);
$finish;
end
end else begin end else begin
$display("Test Complete"); test_end <= 1'b1;
$finish;
end end
end end else begin
check_output <= 1'b0;
end
end end
end end
// Handle Output Data Verification
always @(posedge clk) begin
if (check_output == 1'b1) begin
assert (data_out == data_out_check) else begin
$error("data_out missmatch! recieve: %x != check: %x", data_out, data_out_check);
$finish;
end
assert (data_out_last == data_out_last_check) else begin
$error("data_out_last missmatch! recieve: %x != check: %x", data_out_last, data_out_last_check);
$finish;
end
end
if (test_end == 1'b1) begin
$display("Test Passes");
$finish;
end
end
// File Reading Variables // File Reading Variables
int fd; // File descriptor Handle int fd; // File descriptor Handle
...@@ -222,4 +237,5 @@ module tb_message_build; ...@@ -222,4 +237,5 @@ module tb_message_build;
#10 clk = 1; #10 clk = 1;
end end
end end
endmodule endmodule
\ No newline at end of file
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment