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Commit 408b293d authored by dam1n19's avatar dam1n19
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.gitmodules
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......@@ -19,3 +19,6 @@ url = git@git.soton.ac.uk:soclabs/CHIPKIT.git
[submodule "fpga-lib"]
path = fpga_lib_tech
url = git@git.soton.ac.uk:soclabs/fpga-lib.git
[submodule "rtl_primitives_tech"]
path = rtl_primitives_tech
url = git@git.soton.ac.uk:soclabs/rtl_primitives_tech.git
env/dependency_env.sh
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......@@ -23,6 +23,9 @@ export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator_wrapper_tech"
# NanoSoC
export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc_tech"
# Primtives
export PRIMITIVES_TECH_DIR="$PROJECT_DIR/rtl_primitives_tech"
# FPGA Libraries
export FPGA_LIB_TECH_DIR="$PROJECT_DIR/fpga_lib_tech"
......
flist/primatives/primatives.flist → flist/primitives/primitives.flist
+ 6
− 6
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//-----------------------------------------------------------------------------
// PrimativesFilelist
// Primitives Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
......@@ -9,14 +9,14 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for RTL Primatives
// Abstract : Verilog Command File for RTL Primitives
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/primatives/src/
+incdir+$(PROJECT_DIR)/primatives/src/
// ============= RTL Primitives search path =============
-y $(PRIMITIVES_TECH_DIR)/src/sv/
+incdir+$(PRIMITIVES_TECH_DIR)/src/sv/
$(PROJECT_DIR)/primatives/src/fifo_vr.sv
$(PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
flist/project/system.flist
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......@@ -23,8 +23,8 @@
// ============= System Component Filelist ================
// - Primatives IP
-f $(PROJECT_DIR)/flist/primatives/primatives.flist
// - Primitives IP
-f $(PROJECT_DIR)/flist/primitives/primitives.flist
// - CMSDK IP
-f $(PROJECT_DIR)/flist/ahb/ahb_ip.flist
......
nanosoc_tech @ 88b44d67
Compare 65ff336a...88b44d67
Subproject commit 65ff336af970c2b183bb971966ec444c181ccd70
Subproject commit 88b44d6789aeff477680cee0df9cf63ec5d4e8e7
primatives/src/fifo_vr.sv deleted 100644 → 0
+ 0
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//-----------------------------------------------------------------------------
// SoC Labs Basic Parameterisable Valid-Ready FIFO
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module fifo_vr #(
parameter DEPTH = 4, // FIFO Row Depth
parameter DATA_W = 32, // FIFO Row Width
localparam PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width
)(
input logic clk,
input logic nrst,
input logic en,
// Synchronous, localised reset
input logic sync_rst,
// In (Write) Control
input logic [DATA_W-1:0] data_in,
input logic data_in_last,
input logic data_in_valid,
output logic data_in_ready,
// Out (Read) Control
output logic [DATA_W-1:0] data_out,
output logic data_out_last,
input logic data_out_ready,
output logic data_out_valid,
// Status
output logic [PTR_W-1:0] status_ptr_dif
);
logic data_in_shake; // Successful Write Handshake
logic data_out_shake; // Successful Read Handshake
assign data_in_shake = (data_in_valid == 1'b1) && (data_in_ready == 1'b1);
assign data_out_shake = (data_out_valid == 1'b1) && (data_out_ready == 1'b1);
logic [DATA_W:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
assign ptr_dif = write_ptr - read_ptr;
assign status_ptr_dif = ptr_dif;
// EXAMPLE: Conditions to write and read from FIFO's
// Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read
// 000 - 000 = 000 | Y | N
// 001 - 000 = 001 | Y | Y
// 010 - 000 = 010 | Y | Y
// 011 - 000 = 011 | Y | Y
// 100 - 000 = 100 | N | Y
// 101 - 000 = 101 | N | N
// 110 - 000 = 110 | N | N
// 111 - 000 = 111 | N | N
// WriteValid: WritePtr - ReadPtr < 3'd4
// ReadValid: WritePtr - ReadPtr - 1 < 3'd4
assign {data_out,data_out_last} = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
always_ff @(posedge clk, negedge nrst) begin
if ((!nrst) || sync_rst) begin
// Under Reset
// - Pointers reset to 0 (FIFO is empty without needing to reset the memories)
// - Control taken low
write_ptr <= 0;
read_ptr <= 0;
data_in_ready <= 1'b0;
data_out_valid <= 1'b0;
// Ensure FIFO Values are Known
for (int i = 0; i < DEPTH; i++) begin
fifo[i] <= 'b0;
end
end else if (en == 1'b1) begin
// Enable signal is High
// Write Logic
if (ptr_dif < DEPTH) begin
// Empty Rows in FIFO in FIFO
if (data_in_shake) begin
// Successful Handshake store data in FIFO and increment Write Pointer
fifo [write_ptr[PTR_W-2:0]] <= {data_in,data_in_last};
write_ptr <= write_ptr + 1;
if ((ptr_dif + {{(PTR_W-1){1'b0}},(1'b1 - data_out_shake)}) < DEPTH) begin
// Still space in FIFO after latest write
// If theres a successful read on this clock cycle,
// there will be an additional space in the FIFO next clock cycle
// (number of pieces of data in the FIFO won't have changed)
data_in_ready <= 1'b1;
end else begin
// FIFO is now full
data_in_ready <= 1'b0;
end
end else begin
// Unsuccessful handshake but space in FIFO
// If there's write space now, next cc it will be the same or more
// (more if a succesful read has been carried out in this cc)
data_in_ready <= 1'b1;
end
end else begin
if ((ptr_dif - {{(PTR_W-1){1'b0}}, data_out_shake}) < DEPTH) begin
// If there is a successful read this clock cycle,
// there will be space for another piece of data in the FIFO
// (number of pieces of data in FIFO will have decremented by 1)
data_in_ready <= 1'b1;
end else begin
// FIFO still Full
data_in_ready <= 1'b0;
end
end
// Read Logic
if ((ptr_dif - 1) < DEPTH) begin
// Data in FIFO - atleast one Piece of Data in FIFO
// -> the "-1" causes dif of 0 to wrap where (dif - 1) becomes > DEPTH
if (data_out_shake) begin
// Successful Handshake Increment Read Pointer
read_ptr <= read_ptr + 1;
if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) - 1 < DEPTH) begin
// Still Data in FIFO after latest Read
// If there is a successful write this clock cycle,
// there will be one more piece of data in the FIFO
// (number of pieces of data in FIFO wont have changed)
data_out_valid <= 1'b1;
end else begin
// FIFO empty after latest Read
data_out_valid <= 1'b0;
end
end else begin
// Unsuccessful handshake but Data in FIFO
// If there's read data now, next cc it will be the same or more
// (more if a succesful write has been carried out in this cc)
data_out_valid <= 1'b1;
end
end else begin
if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) < DEPTH) begin
// If there is a successful write this clock cycle,
// there will be one more piece of data in the FIFO
// (number of pieces of data in FIFO will have incremented by 1)
data_out_valid <= 1'b1;
end else begin
// FIFO still empty
data_out_valid <= 1'b0;
end
end
end else begin
// If Enable is Low, set Control Low
data_in_ready <= 1'b0;
data_out_valid <= 1'b0;
end
end
// Verif Notes to Check behaiour:
// 1) Fill FIFO up with Data
// 2) Read & Write in same clock cycle
endmodule
proj-branch
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......@@ -10,10 +10,11 @@
#-----------------------------------------------------------------------------
# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
# Project Repository Subrepository Branch Index
secworks-sha256: main
nanosoc_tech: main
chipkit_flow: main
accelerator_wrapper_tech: main
fpga_lib_tech: main
generic_lib_tech: main
secworks-sha256: main
rtl_primitives_tech: main
socsim_flow: main
\ No newline at end of file
rtl_primitives_tech @ ce27da6f
Subproject commit ce27da6f556a7dd20bcce213278e6f29b8d66332
secworks-sha256 @ 0ca2ab83
Compare 0ca2ab83...0ca2ab83
Subproject commit 0ca2ab834833789eb49f8f61d929a80734b3f990
system/README.md 0 → 100644
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wrapper/README.md 0 → 100644
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View file @ 408b293d
This directory is for the custom design and verification files for an accelerator wrapper.
By using the accelerator_wrapper_tech components, Arm IP and the IP components provided by your own accelerator, it should be possible to construct a wrapped up version of your accelerator which can then be plumbed into the expansion region of the NanoSoC Expansion Region.
The src directory is where the design files should go. Then within the flist directory at the top-level of this repository, under project, you should list your accelerator components within your accelerator.flist file.
\ No newline at end of file
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