diff --git a/.gitmodules b/.gitmodules
index 72c7f19aa1fe8caa247147fde9a99a5722058f56..5c3b3357028b3bf665dcfc69de4f6bd28f8fde10 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -19,3 +19,6 @@ url = git@git.soton.ac.uk:soclabs/CHIPKIT.git
[submodule "fpga-lib"]
path = fpga_lib_tech
url = git@git.soton.ac.uk:soclabs/fpga-lib.git
+[submodule "rtl_primitives_tech"]
+ path = rtl_primitives_tech
+ url = git@git.soton.ac.uk:soclabs/rtl_primitives_tech.git
diff --git a/env/dependency_env.sh b/env/dependency_env.sh
index edff88561cf965848cf4d22f53e2e2a7bb706117..bbea7d7b90d091e67e7c5f87f11215317a8d2195 100755
--- a/env/dependency_env.sh
+++ b/env/dependency_env.sh
@@ -23,6 +23,9 @@ export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator_wrapper_tech"
# NanoSoC
export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc_tech"
+# Primtives
+export PRIMITIVES_TECH_DIR="$PROJECT_DIR/rtl_primitives_tech"
+
# FPGA Libraries
export FPGA_LIB_TECH_DIR="$PROJECT_DIR/fpga_lib_tech"
diff --git a/flist/primatives/primatives.flist b/flist/primitives/primitives.flist
similarity index 70%
rename from flist/primatives/primatives.flist
rename to flist/primitives/primitives.flist
index 987baf885f8e52ee5b18e90835f335b62a342e8b..807360c5ee45cf131e09da095ce9827a32f88fc4 100644
--- a/flist/primatives/primatives.flist
+++ b/flist/primitives/primitives.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// PrimativesFilelist
+// Primitives Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,14 +9,14 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for RTL Primatives
+// Abstract : Verilog Command File for RTL Primitives
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-// ============= Accelerator Module search path =============
--y $(PROJECT_DIR)/primatives/src/
-+incdir+$(PROJECT_DIR)/primatives/src/
+// ============= RTL Primitives search path =============
+-y $(PRIMITIVES_TECH_DIR)/src/sv/
++incdir+$(PRIMITIVES_TECH_DIR)/src/sv/
-$(PROJECT_DIR)/primatives/src/fifo_vr.sv
+$(PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
diff --git a/flist/project/system.flist b/flist/project/system.flist
index d95e9b3c098f8691c90566f2b3935929c96528ce..4210f836a3a4c84c3b31ad6190ccbbd01056803a 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -23,8 +23,8 @@
// ============= System Component Filelist ================
-// - Primatives IP
--f $(PROJECT_DIR)/flist/primatives/primatives.flist
+// - Primitives IP
+-f $(PROJECT_DIR)/flist/primitives/primitives.flist
// - CMSDK IP
-f $(PROJECT_DIR)/flist/ahb/ahb_ip.flist
diff --git a/nanosoc_tech b/nanosoc_tech
index 65ff336af970c2b183bb971966ec444c181ccd70..88b44d6789aeff477680cee0df9cf63ec5d4e8e7 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 65ff336af970c2b183bb971966ec444c181ccd70
+Subproject commit 88b44d6789aeff477680cee0df9cf63ec5d4e8e7
diff --git a/primatives/src/fifo_vr.sv b/primatives/src/fifo_vr.sv
deleted file mode 100644
index b86b9d45ebd5bc4c2275496f4a30b46173f4496e..0000000000000000000000000000000000000000
--- a/primatives/src/fifo_vr.sv
+++ /dev/null
@@ -1,162 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Parameterisable Valid-Ready FIFO
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module fifo_vr #(
- parameter DEPTH = 4, // FIFO Row Depth
- parameter DATA_W = 32, // FIFO Row Width
- localparam PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width
-)(
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // In (Write) Control
- input logic [DATA_W-1:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Out (Read) Control
- output logic [DATA_W-1:0] data_out,
- output logic data_out_last,
- input logic data_out_ready,
- output logic data_out_valid,
-
- // Status
- output logic [PTR_W-1:0] status_ptr_dif
-);
-
- logic data_in_shake; // Successful Write Handshake
- logic data_out_shake; // Successful Read Handshake
-
- assign data_in_shake = (data_in_valid == 1'b1) && (data_in_ready == 1'b1);
- assign data_out_shake = (data_out_valid == 1'b1) && (data_out_ready == 1'b1);
-
- logic [DATA_W:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
- logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
- logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
- logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
-
- assign ptr_dif = write_ptr - read_ptr;
-
- assign status_ptr_dif = ptr_dif;
-
- // EXAMPLE: Conditions to write and read from FIFO's
- // Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read
- // 000 - 000 = 000 | Y | N
- // 001 - 000 = 001 | Y | Y
- // 010 - 000 = 010 | Y | Y
- // 011 - 000 = 011 | Y | Y
- // 100 - 000 = 100 | N | Y
- // 101 - 000 = 101 | N | N
- // 110 - 000 = 110 | N | N
- // 111 - 000 = 111 | N | N
- // WriteValid: WritePtr - ReadPtr < 3'd4
- // ReadValid: WritePtr - ReadPtr - 1 < 3'd4
-
- assign {data_out,data_out_last} = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
-
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) || sync_rst) begin
- // Under Reset
- // - Pointers reset to 0 (FIFO is empty without needing to reset the memories)
- // - Control taken low
- write_ptr <= 0;
- read_ptr <= 0;
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- // Ensure FIFO Values are Known
- for (int i = 0; i < DEPTH; i++) begin
- fifo[i] <= 'b0;
- end
- end else if (en == 1'b1) begin
- // Enable signal is High
- // Write Logic
- if (ptr_dif < DEPTH) begin
- // Empty Rows in FIFO in FIFO
- if (data_in_shake) begin
- // Successful Handshake store data in FIFO and increment Write Pointer
- fifo [write_ptr[PTR_W-2:0]] <= {data_in,data_in_last};
- write_ptr <= write_ptr + 1;
- if ((ptr_dif + {{(PTR_W-1){1'b0}},(1'b1 - data_out_shake)}) < DEPTH) begin
- // Still space in FIFO after latest write
- // If theres a successful read on this clock cycle,
- // there will be an additional space in the FIFO next clock cycle
- // (number of pieces of data in the FIFO won't have changed)
- data_in_ready <= 1'b1;
- end else begin
- // FIFO is now full
- data_in_ready <= 1'b0;
- end
- end else begin
- // Unsuccessful handshake but space in FIFO
- // If there's write space now, next cc it will be the same or more
- // (more if a succesful read has been carried out in this cc)
- data_in_ready <= 1'b1;
- end
- end else begin
- if ((ptr_dif - {{(PTR_W-1){1'b0}}, data_out_shake}) < DEPTH) begin
- // If there is a successful read this clock cycle,
- // there will be space for another piece of data in the FIFO
- // (number of pieces of data in FIFO will have decremented by 1)
- data_in_ready <= 1'b1;
- end else begin
- // FIFO still Full
- data_in_ready <= 1'b0;
- end
- end
- // Read Logic
- if ((ptr_dif - 1) < DEPTH) begin
- // Data in FIFO - atleast one Piece of Data in FIFO
- // -> the "-1" causes dif of 0 to wrap where (dif - 1) becomes > DEPTH
- if (data_out_shake) begin
- // Successful Handshake Increment Read Pointer
- read_ptr <= read_ptr + 1;
- if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) - 1 < DEPTH) begin
- // Still Data in FIFO after latest Read
- // If there is a successful write this clock cycle,
- // there will be one more piece of data in the FIFO
- // (number of pieces of data in FIFO wont have changed)
- data_out_valid <= 1'b1;
- end else begin
- // FIFO empty after latest Read
- data_out_valid <= 1'b0;
- end
- end else begin
- // Unsuccessful handshake but Data in FIFO
- // If there's read data now, next cc it will be the same or more
- // (more if a succesful write has been carried out in this cc)
- data_out_valid <= 1'b1;
- end
- end else begin
- if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) < DEPTH) begin
- // If there is a successful write this clock cycle,
- // there will be one more piece of data in the FIFO
- // (number of pieces of data in FIFO will have incremented by 1)
- data_out_valid <= 1'b1;
- end else begin
- // FIFO still empty
- data_out_valid <= 1'b0;
- end
- end
- end else begin
- // If Enable is Low, set Control Low
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- end
- end
-
- // Verif Notes to Check behaiour:
- // 1) Fill FIFO up with Data
- // 2) Read & Write in same clock cycle
-endmodule
diff --git a/proj-branch b/proj-branch
index b2f0b5b3da08e5e433e853fc029d00f6cfdcd708..973fbbceed90565ce04e3be3772c82dbc2913301 100644
--- a/proj-branch
+++ b/proj-branch
@@ -10,10 +10,11 @@
#-----------------------------------------------------------------------------
# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
# Project Repository Subrepository Branch Index
+secworks-sha256: main
nanosoc_tech: main
chipkit_flow: main
accelerator_wrapper_tech: main
fpga_lib_tech: main
generic_lib_tech: main
-secworks-sha256: main
+rtl_primitives_tech: main
socsim_flow: main
\ No newline at end of file
diff --git a/rtl_primitives_tech b/rtl_primitives_tech
new file mode 160000
index 0000000000000000000000000000000000000000..ce27da6f556a7dd20bcce213278e6f29b8d66332
--- /dev/null
+++ b/rtl_primitives_tech
@@ -0,0 +1 @@
+Subproject commit ce27da6f556a7dd20bcce213278e6f29b8d66332
diff --git a/secworks-sha256 b/secworks-sha256
deleted file mode 160000
index 0ca2ab834833789eb49f8f61d929a80734b3f990..0000000000000000000000000000000000000000
--- a/secworks-sha256
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0ca2ab834833789eb49f8f61d929a80734b3f990
diff --git a/system/README.md b/system/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/wrapper/README.md b/wrapper/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..86cdfac35aca8b168e169d431ee0deb78e062c25
--- /dev/null
+++ b/wrapper/README.md
@@ -0,0 +1,5 @@
+This directory is for the custom design and verification files for an accelerator wrapper.
+
+By using the accelerator_wrapper_tech components, Arm IP and the IP components provided by your own accelerator, it should be possible to construct a wrapped up version of your accelerator which can then be plumbed into the expansion region of the NanoSoC Expansion Region.
+
+The src directory is where the design files should go. Then within the flist directory at the top-level of this repository, under project, you should list your accelerator components within your accelerator.flist file.
\ No newline at end of file