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ASIC/TSMC28nm/no_pins/Synopsys_FC/init_placement.tcl 0 → 100644
View file @ 02f873a7
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
set_temperature -40 -min 125 -corners default
set_voltage 0.99 -min 0.81 -corners default
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
explore_logic_hierarchy -place -rectangular
save_lib nanosoc_chip_pads.dlib
ASIC/TSMC28nm/no_pins/Synopsys_FC/power_plan.tcl 0 → 100644
View file @ 02f873a7
connect_pg_net -automatic
create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
-vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
{{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core
set_pg_strategy std_cell_strat -core -pattern {{name: std_pattern} {nets: {VDD VSS}}}
compile_pg -strategies core_ring
compile_pg -strategies M5M8_mesh
compile_pg -strategies std_cell_strat
ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl
View file @ 02f873a7
set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
# Technology files
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf
set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.lef
set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf
set cln28ht_lef_file $cln28ht_tech_path/lef/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.lef
# Standard Cell libraries
set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
set sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
set sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
set sc9mcpp140z_db_file_ff_0p99v_m40C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
set sc9mcpp140z_db_file $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
# SRAM files (using Arm compiler)
set sram_16k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
set sram_16k_lef_file $sram_16k_path/sram_16k.lef
set sram_16k_gds_file $sram_16k_path/sram_16k.gds2
set sram_16k_lib_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
set sram_16k_lib_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_16k_db_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
set sram_16k_db_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
create_physical_lib -technology $cln28ht_tech_file cln28ht
read_lef -library cln28ht $sc9mcpp140z_lef_file
read_gds -library cln28ht $sc9mcpp140z_gds_file
set_cell_site -site_def unit
update_physical_properties -library cln28ht -format clf -file $sc9mcpp140z_antenna_file
# ROM Files (using arm Compiler)
set rom_path $env(SOCLABS_PROJECT_DIR)/memories/bootrom
set rom_via_lef_file $rom_path/rom_via.lef
set rom_via_gds_file $rom_path/rom_via.gds2
set rom_via_lib_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
set rom_via_lib_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
set rom_via_lib_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
set rom_via_db_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
set rom_via_db_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
set rom_via_db_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
update_physical_properties -library cln28ht -format db -file $sc9mcpp140z_db_file
create_frame
# Create standard cell fusion library
create_fusion_lib -dbs [list $sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $sc9mcpp140z_lef_file] -technology $cln28ht_tech_file cln28ht
save_fusion_lib cln28ht
set_app_options -name
close_fusion_lib cln28ht
write_physical_lib -output cln28ht.ndm
report_lib -all cln28ht
# 16K SRAM
read_lib $sram_16k_lib_file_ss_0p81v_125c
write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
set_check_library_options -logic_vs_physical -physical
check_library -physical_library_name cln28ht -logic_library_name $sc9mcpp140z_db_file
\ No newline at end of file
read_lib $sram_16k_lib_file_tt_0p90v_25c
write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
close_lib -all
read_lib $sram_16k_lib_file_ff_0p99v_m40c
write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
save_fusion_lib sram_16k
close_fusion_lib sram_16k
# Boot ROM
read_lib $rom_via_lib_file_ss_0p81v_125c
write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
read_lib $rom_via_lib_file_tt_0p90v_25c
write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
close_lib -all
read_lib $rom_via_lib_file_ff_0p99v_m40c
write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $rom_via_db_file_ss_0p81v_125c $rom_via_db_file_tt_0p90v_25c $rom_via_db_file_ff_0p99v_m40c] -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
save_fusion_lib rom_via
close_fusion_lib rom_via
exit
\ No newline at end of file
ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
View file @ 02f873a7
......@@ -224,122 +224,101 @@ nanosoc_chip_cfg #(
// Pad IO power supplies
PVDD2CDG uPAD_VDDIO_0(
PVDD2DGZ_H_G uPAD_VDDIO_0(
.VDDPST(VDDIO)
);
//PVDD2CDG uPAD_VDDIO_1(
// .VDDPST(VDDIO)
// );
PVDD2CDG uPAD_VDDIO_2(
PVDD2DGZ_H_G uPAD_VDDIO_2(
.VDDPST(VDDIO)
);
PVDD2POC uPAD_VDDIO_3(
PVDD2POC_H_G uPAD_VDDIO_3(
.VDDPST(VDDIO)
);
PVSS2CDG uPAD_VSSIO_0(
PVSS2DGZ_H_G uPAD_VSSIO_0(
.VSSPST(VSSIO)
);
PVSS2CDG uPAD_VSSIO_1(
PVSS2DGZ_H_G uPAD_VSSIO_1(
.VSSPST(VSSIO)
);
// Core power supplies
PVDD1CDG uPAD_VDD_0(
PVDD1DGZ_H_G uPAD_VDD_0(
.VDD(VDD)
);
PVDD1CDG uPAD_VDD_1(
PVDD1DGZ_V_G uPAD_VDD_1(
.VDD(VDD)
);
PVDD1CDG uPAD_VDD_2(
PVDD1DGZ_H_G uPAD_VDD_2(
.VDD(VDD)
);
PVDD1CDG uPAD_VDD_3(
PVDD1DGZ_V_G uPAD_VDD_3(
.VDD(VDD)
);
PVSS1CDG uPAD_VSS_0(
PVSS1DGZ_H_G uPAD_VSS_0(
.VSS(VSS)
);
PVSS1CDG uPAD_VSS_1(
PVSS1DGZ_V_G uPAD_VSS_1(
.VSS(VSS)
);
PVSS1CDG uPAD_VSS_2(
PVSS1DGZ_H_G uPAD_VSS_2(
.VSS(VSS)
);
PVSS1CDG uPAD_VSS_3(
PVSS1DGZ_V_G uPAD_VSS_3(
.VSS(VSS)
);
// Accelerator Power supplies
PVDD1CDG uPAD_VDDACC_0(
PVDD1DGZ_H_G uPAD_VDDACC_0(
.VDD(VDDACC)
);
PVDD1CDG uPAD_VDDACC_1(
PVDD1DGZ_V_G uPAD_VDDACC_1(
.VDD(VDDACC)
);
PVDD1CDG uPAD_VDDACC_2(
PVDD1DGZ_H_G uPAD_VDDACC_2(
.VDD(VDDACC)
);
// Clock, Reset and Serial Wire Debug ports
PRDW0408SCDG uPAD_SE_I (
.IE(tiehi),
PRDW08SDGZ_V_G uPAD_SE_I (
.C(pad_se_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(SE)
);
PRDW0408SCDG uPAD_CLK_I (
.IE(tiehi),
PRDW08SDGZ_V_G uPAD_CLK_I (
.C(pad_clk_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(CLK)
);
PRDW0408SCDG uPAD_TEST_I (
.IE(tiehi),
PRDW08SDGZ_V_G uPAD_TEST_I (
.C(pad_test_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(TEST)
);
PRDW0408SCDG uPAD_NRST_I (
.IE(tiehi),
PRDW08SDGZ_V_G uPAD_NRST_I (
.C(pad_nrst_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(NRST)
);
PRDW0408SCDG uPAD_SWDIO_IO (
.IE(pad_swdio_z),
PRDW08SDGZ_V_G uPAD_SWDIO_IO (
.C(pad_swdio_i),
.PE(tielo),
.DS(tielo),
.I(pad_swdio_o),
.OEN(pad_swdio_z),
.PAD(SWDIO)
);
PRDW0408SCDG uPAD_SWDCK_I (
.IE(tiehi),
PRDW08SDGZ_V_G uPAD_SWDCK_I (
.C(pad_swdclk_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(SWDCK)
......@@ -347,162 +326,114 @@ PRDW0408SCDG uPAD_SWDCK_I (
// GPI.I Port 0 x 16
PRDW0408SCDG uPAD_P0_00 (
.IE(pad_gpio_port0_z[00]),
PRDW08SDGZ_V_G uPAD_P0_00 (
.C(pad_gpio_port0_i[00]),
.PE(pad_gpio_port0_z[00]&pad_gpio_port0_o[00]),
.DS(tielo),
.I(pad_gpio_port0_o[00]),
.OEN(pad_gpio_port0_z[00]),
.PAD(P0[00])
);
PRDW0408SCDG uPAD_P0_01 (
.IE(pad_gpio_port0_z[01]),
PRDW08SDGZ_V_G uPAD_P0_01 (
.C(pad_gpio_port0_i[01]),
.PE(pad_gpio_port0_z[01]&pad_gpio_port0_o[01]),
.DS(tielo),
.I(pad_gpio_port0_o[01]),
.OEN(pad_gpio_port0_z[01]),
.PAD(P0[01])
);
PRDW0408SCDG uPAD_P0_02 (
.IE(pad_gpio_port0_z[02]),
PRDW08SDGZ_V_G uPAD_P0_02 (
.C(pad_gpio_port0_i[02]),
.PE(pad_gpio_port0_z[02]&pad_gpio_port0_o[02]),
.DS(tielo),
.I(pad_gpio_port0_o[02]),
.OEN(pad_gpio_port0_z[02]),
.PAD(P0[02])
);
PRDW0408SCDG uPAD_P0_03 (
.IE(pad_gpio_port0_z[03]),
PRDW08SDGZ_V_G uPAD_P0_03 (
.C(pad_gpio_port0_i[03]),
.PE(pad_gpio_port0_z[03]&pad_gpio_port0_o[03]),
.DS(tielo),
.I(pad_gpio_port0_o[03]),
.OEN(pad_gpio_port0_z[03]),
.PAD(P0[03])
);
PRDW0408SCDG uPAD_P0_04 (
.IE(pad_gpio_port0_z[04]),
PRDW08SDGZ_V_G uPAD_P0_04 (
.C(pad_gpio_port0_i[04]),
.PE(pad_gpio_port0_z[04]&pad_gpio_port0_o[04]),
.DS(tielo),
.I(pad_gpio_port0_o[04]),
.OEN(pad_gpio_port0_z[04]),
.PAD(P0[04])
);
PRDW0408SCDG uPAD_P0_05 (
.IE(pad_gpio_port0_z[05]),
PRDW08SDGZ_V_G uPAD_P0_05 (
.C(pad_gpio_port0_i[05]),
.PE(pad_gpio_port0_z[05]&pad_gpio_port0_o[05]),
.DS(tielo),
.I(pad_gpio_port0_o[05]),
.OEN(pad_gpio_port0_z[05]),
.PAD(P0[05])
);
PRDW0408SCDG uPAD_P0_06 (
.IE(pad_gpio_port0_z[06]),
PRDW08SDGZ_V_G uPAD_P0_06 (
.C(pad_gpio_port0_i[06]),
.PE(pad_gpio_port0_z[06]&pad_gpio_port0_o[06]),
.DS(tielo),
.I(pad_gpio_port0_o[06]),
.OEN(pad_gpio_port0_z[06]),
.PAD(P0[06])
);
PRDW0408SCDG uPAD_P0_07 (
.IE(pad_gpio_port0_z[07]),
PRDW08SDGZ_V_G uPAD_P0_07 (
.C(pad_gpio_port0_i[07]),
.PE(pad_gpio_port0_z[07]&pad_gpio_port0_o[07]),
.DS(tielo),
.I(pad_gpio_port0_o[07]),
.OEN(pad_gpio_port0_z[07]),
.PAD(P0[07])
);
// GPI.I Port 1 x 16
PRDW0408SCDG uPAD_P1_00 (
.IE(pad_gpio_port1_z[00]),
PRDW08SDGZ_V_G uPAD_P1_00 (
.C(pad_gpio_port1_i[00]),
.PE(pad_gpio_port1_z[00]&pad_gpio_port1_o[00]),
.DS(tielo),
.I(pad_gpio_port1_o[00]),
.OEN(pad_gpio_port1_z[00]),
.PAD(P1[00])
);
PRDW0408SCDG uPAD_P1_01 (
.IE(pad_gpio_port1_z[01]),
PRDW08SDGZ_V_G uPAD_P1_01 (
.C(pad_gpio_port1_i[01]),
.PE(pad_gpio_port1_z[01]&pad_gpio_port1_o[01]),
.DS(tielo),
.I(pad_gpio_port1_o[01]),
.OEN(pad_gpio_port1_z[01]),
.PAD(P1[01])
);
PRDW0408SCDG uPAD_P1_02 (
.IE(pad_gpio_port1_z[02]),
PRDW08SDGZ_V_G uPAD_P1_02 (
.C(pad_gpio_port1_i[02]),
.PE(pad_gpio_port1_z[02]&pad_gpio_port1_o[02]),
.DS(tielo),
.I(pad_gpio_port1_o[02]),
.OEN(pad_gpio_port1_z[02]),
.PAD(P1[02])
);
PRDW0408SCDG uPAD_P1_03 (
.IE(pad_gpio_port1_z[03]),
PRDW08SDGZ_V_G uPAD_P1_03 (
.C(pad_gpio_port1_i[03]),
.PE(pad_gpio_port1_z[03]&pad_gpio_port1_o[03]),
.DS(tielo),
.I(pad_gpio_port1_o[03]),
.OEN(pad_gpio_port1_z[03]),
.PAD(P1[03])
);
PRDW0408SCDG uPAD_P1_04 (
.IE(pad_gpio_port1_z[04]),
PRDW08SDGZ_V_G uPAD_P1_04 (
.C(pad_gpio_port1_i[04]),
.PE(pad_gpio_port1_z[04]&pad_gpio_port1_o[04]),
.DS(tielo),
.I(pad_gpio_port1_o[04]),
.OEN(pad_gpio_port1_z[04]),
.PAD(P1[04])
);
PRDW0408SCDG uPAD_P1_05 (
.IE(pad_gpio_port1_z[05]),
PRDW08SDGZ_V_G uPAD_P1_05 (
.C(pad_gpio_port1_i[05]),
.PE(pad_gpio_port1_z[05]&pad_gpio_port1_o[05]),
.DS(tielo),
.I(pad_gpio_port1_o[05]),
.OEN(pad_gpio_port1_z[05]),
.PAD(P1[05])
);
PRDW0408SCDG uPAD_P1_06 (
.IE(pad_gpio_port1_z[06]),
PRDW08SDGZ_V_G uPAD_P1_06 (
.C(pad_gpio_port1_i[06]),
.PE(pad_gpio_port1_z[06]&pad_gpio_port1_o[06]),
.DS(tielo),
.I(pad_gpio_port1_o[06]),
.OEN(pad_gpio_port1_z[06]),
.PAD(P1[06])
);
PRDW0408SCDG uPAD_P1_07 (
.IE(pad_gpio_port1_z[07]),
PRDW08SDGZ_V_G uPAD_P1_07 (
.C(pad_gpio_port1_i[07]),
.PE(pad_gpio_port1_z[07]&pad_gpio_port1_o[07]),
.DS(tielo),
.I(pad_gpio_port1_o[07]),
.OEN(pad_gpio_port1_z[07]),
.PAD(P1[07])
......
ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v 0 → 100644
View file @ 02f873a7
//-----------------------------------------------------------------------------
// customised top-level Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
module nanosoc_chip_pads (
`ifdef POWER_PINS
inout wire VDDIO,
inout wire VSSIO,
inout wire VDD,
inout wire VSS,
inout wire VDDACC,
`endif
input wire SE,
inout wire CLK, // input
inout wire TEST, // output
inout wire NRST, // active low reset
inout wire [15:0] P0,
inout wire [15:0] P1,
inout wire SWDIO,
inout wire SWDCK);
//------------------------------------
// internal wires
localparam GPIO_TIO = 4;
wire pad_clk_i;
wire pad_nrst_i;
wire pad_test_i;
wire pad_swdclk_i;
wire pad_swdio_i;
wire pad_swdio_o;
wire pad_swdio_e;
wire pad_swdio_z;
wire [15:0] pad_gpio_port0_i ;
wire [15:0] pad_gpio_port0_o ;
wire [15:0] pad_gpio_port0_e ;
wire [15:0] pad_gpio_port0_z ;
wire [15:0] pad_gpio_port1_i ;
wire [15:0] pad_gpio_port1_o ;
wire [15:0] pad_gpio_port1_e ;
wire [15:0] pad_gpio_port1_z ;
wire soc_nreset;
wire soc_diag_mode;
wire soc_diag_ctrl;
wire soc_scan_mode;
wire soc_scan_enable;
wire [GPIO_TIO-1:0] soc_scan_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_scan_out; //soc test status outputs
wire soc_bist_mode;
wire soc_bist_enable;
wire [GPIO_TIO-1:0] soc_bist_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_bist_out; //soc test status outputs
wire soc_alt_mode; // ALT MODE = UART
wire soc_uart_rxd_i; // UART RXD
wire soc_uart_txd_o; // UART TXD
wire soc_swd_mode; // SWD mode
wire soc_swd_clk_i; // SWDCLK
wire soc_swd_dio_i; // SWDIO tristate input
wire soc_swd_dio_o; // SWDIO trstate output
wire soc_swd_dio_e; // SWDIO tristate output enable
wire soc_swd_dio_z; // SWDIO tristate output hiz
wire [15:0] soc_gpio_port0_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port0_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port0_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port0_z; // GPIO SOC tristate output hiz
wire [15:0] soc_gpio_port1_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
wire pad_se_i;
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
assign pad_gpio_port0_e[15:GPIO_TIO] = soc_gpio_port0_e[15:GPIO_TIO];
assign pad_gpio_port0_z[15:GPIO_TIO] = soc_gpio_port0_z[15:GPIO_TIO];
assign soc_gpio_port1_i[15:GPIO_TIO] = pad_gpio_port1_i[15:GPIO_TIO];
assign pad_gpio_port1_o[15:GPIO_TIO] = soc_gpio_port1_o[15:GPIO_TIO];
assign pad_gpio_port1_e[15:GPIO_TIO] = soc_gpio_port1_e[15:GPIO_TIO];
assign pad_gpio_port1_z[15:GPIO_TIO] = soc_gpio_port1_z[15:GPIO_TIO];
wire tiehi = 1'b1;
wire tielo = 1'b0;
nanosoc_chip_cfg #(
.GPIO_TIO (GPIO_TIO)
)
u_nanosoc_chip_cfg
(
// Primary Inputs
.pad_clk_i (pad_clk_i )
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
,.pad_altin_i (pad_se_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
,.pad_altio_z (pad_swdio_z ) // SWDIO/UARTTXD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-0 (user)
,.pad_gpio_port0_i (pad_gpio_port0_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port0_o (pad_gpio_port0_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port0_e (pad_gpio_port0_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port0_z (pad_gpio_port0_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-1 (system)
,.pad_gpio_port1_i (pad_gpio_port1_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port1_o (pad_gpio_port1_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port1_e (pad_gpio_port1_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port1_z (pad_gpio_port1_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
//SOC
,.soc_nreset (soc_nreset )
,.soc_diag_mode (soc_diag_mode )
,.soc_diag_ctrl (soc_diag_ctrl )
,.soc_scan_mode (soc_scan_mode )
,.soc_scan_enable (soc_scan_enable )
,.soc_scan_in (soc_scan_in ) // soc test scan chain inputs
,.soc_scan_out (soc_scan_out ) // soc test scan chain outputs
,.soc_bist_mode (soc_bist_mode )
,.soc_bist_enable (soc_bist_enable )
,.soc_bist_in (soc_bist_in ) // soc bist control inputs
,.soc_bist_out (soc_bist_out ) // soc test status outputs
,.soc_alt_mode (soc_alt_mode )// ALT MODE = UART
,.soc_uart_rxd_i (soc_uart_rxd_i ) // UART RXD
,.soc_uart_txd_o (soc_uart_txd_o ) // UART TXD
,.soc_swd_mode (soc_swd_mode ) // SWD mode
,.soc_swd_clk_i (soc_swd_clk_i ) // SWDCLK
,.soc_swd_dio_i (soc_swd_dio_i ) // SWDIO tristate input
,.soc_swd_dio_o (soc_swd_dio_o ) // SWDIO trstate output
,.soc_swd_dio_e (soc_swd_dio_e ) // SWDIO tristate output enable
,.soc_swd_dio_z (soc_swd_dio_z ) // SWDIO tristate output hiz
,.soc_gpio_port0_i (soc_gpio_port0_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port0_o (soc_gpio_port0_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port0_e (soc_gpio_port0_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port0_z (soc_gpio_port0_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
,.soc_gpio_port1_i (soc_gpio_port1_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port1_o (soc_gpio_port1_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port1_e (soc_gpio_port1_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port1_z (soc_gpio_port1_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
);
// --------------------------------------------------------------------------------
// Cortex-M0 nanosoc Microcontroller
// --------------------------------------------------------------------------------
nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS
.VDD (VDD),
.VSS (VSS),
.VDDACC (VDDACC),
`endif
//`ifdef ASIC_TEST_PORTS
.diag_mode (soc_diag_mode ),
.diag_ctrl (soc_diag_ctrl ),
.scan_mode (soc_scan_mode ),
.scan_enable (soc_scan_enable ),
.scan_in (soc_scan_in ), // soc test scan chain inputs
.scan_out (soc_scan_out ), // soc test scan chain outputs
.bist_mode (soc_bist_mode ),
.bist_enable (soc_bist_enable ),
.bist_in (soc_bist_in ), // soc bist control inputs
.bist_out (soc_bist_out ), // soc test status outputs
.alt_mode (soc_alt_mode ),// ALT MODE = UART
.uart_rxd_i (soc_uart_rxd_i ), // UART RXD
.uart_txd_o (soc_uart_txd_o ), // UART TXD
.swd_mode (soc_swd_mode ), // SWD mode
//`endif
.clk_i (pad_clk_i),
.test_i (soc_scan_mode), //(test_i),
.nrst_i (soc_nreset), //(nrst_i),
.p0_i (soc_gpio_port0_i), // level-shifted input from pad
.p0_o (soc_gpio_port0_o), // output port drive
.p0_e (soc_gpio_port0_e), // active high output drive enable (pad tech dependent)
.p0_z (soc_gpio_port0_z), // active low output drive enable (pad tech dependent)
.p1_i (soc_gpio_port1_i), // level-shifted input from pad
.p1_o (soc_gpio_port1_o), // output port drive
.p1_e (soc_gpio_port1_e), // active high output drive enable (pad tech dependent)
.p1_z (soc_gpio_port1_z), // active low output drive enable (pad tech dependent)
.swdio_i (soc_swd_dio_i),
.swdio_o (soc_swd_dio_o),
.swdio_e (soc_swd_dio_e),
.swdio_z (soc_swd_dio_z),
.swdclk_i (pad_swdclk_i)
);
// --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping)
// --------------------------------------------------------------------------------
`ifdef POWER_PINS
// Pad IO power supplies
PAD_VDDIO uPAD_VDDIO_1(
.PAD(VDDIO)
);
PAD_VSSIO uPAD_VSSIO_1(
.PAD(VSSIO)
);
// Core power supplies
PAD_VDDSOC uPAD_VDD_1(
.PAD(VDD)
);
PAD_VSS uPAD_VSS_1(
.PAD(VSS)
);
// Accelerator Power supplies
PAD_VDDSOC uPAD_VDDACC_1(
.PAD(VDDACC)
);
`endif
// Clock, Reset and Serial Wire Debug ports
PAD_INOUT8MA_NOE uPAD_SE_I (
.PAD (SE),
.O (tielo),
.I (pad_se_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_CLK_I (
.PAD (CLK),
.O (tielo),
.I (pad_clk_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_XTAL_I (
.PAD (TEST),
.O (tielo),
.I (pad_test_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_NRST_I (
.PAD (NRST),
.O (tielo),
.I (pad_nrst_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_SWDIO_IO (
.PAD (SWDIO),
.O (pad_swdio_o),
.I (pad_swdio_i),
.NOE (pad_swdio_z)
);
PAD_INOUT8MA_NOE uPAD_SWDCK_I (
.PAD (SWDCK),
.O (tielo),
.I (pad_swdclk_i),
.NOE (tiehi)
);
// GPI.I Port 0 x 16
PAD_INOUT8MA_NOE uPAD_P0_00 (
.PAD (P0[00]),
.O (pad_gpio_port0_o[00]),
.I (pad_gpio_port0_i[00]),
.NOE (pad_gpio_port0_z[00])
);
PAD_INOUT8MA_NOE uPAD_P0_01 (
.PAD (P0[01]),
.O (pad_gpio_port0_o[01]),
.I (pad_gpio_port0_i[01]),
.NOE (pad_gpio_port0_z[01])
);
PAD_INOUT8MA_NOE uPAD_P0_02 (
.PAD (P0[02]),
.O (pad_gpio_port0_o[02]),
.I (pad_gpio_port0_i[02]),
.NOE (pad_gpio_port0_z[02])
);
PAD_INOUT8MA_NOE uPAD_P0_03 (
.PAD (P0[03]),
.O (pad_gpio_port0_o[03]),
.I (pad_gpio_port0_i[03]),
.NOE (pad_gpio_port0_z[03])
);
PAD_INOUT8MA_NOE uPAD_P0_04 (
.PAD (P0[04]),
.O (pad_gpio_port0_o[04]),
.I (pad_gpio_port0_i[04]),
.NOE (pad_gpio_port0_z[04])
);
PAD_INOUT8MA_NOE uPAD_P0_05 (
.PAD (P0[05]),
.O (pad_gpio_port0_o[05]),
.I (pad_gpio_port0_i[05]),
.NOE (pad_gpio_port0_z[05])
);
PAD_INOUT8MA_NOE uPAD_P0_06 (
.PAD (P0[06]),
.O (pad_gpio_port0_o[06]),
.I (pad_gpio_port0_i[06]),
.NOE (pad_gpio_port0_z[06])
);
PAD_INOUT8MA_NOE uPAD_P0_07 (
.PAD (P0[07]),
.O (pad_gpio_port0_o[07]),
.I (pad_gpio_port0_i[07]),
.NOE (pad_gpio_port0_z[07])
);
PAD_INOUT8MA_NOE uPAD_P0_08 (
.PAD (P0[08]),
.O (pad_gpio_port0_o[08]),
.I (pad_gpio_port0_i[08]),
.NOE (pad_gpio_port0_z[08])
);
PAD_INOUT8MA_NOE uPAD_P0_09 (
.PAD (P0[09]),
.O (pad_gpio_port0_o[09]),
.I (pad_gpio_port0_i[09]),
.NOE (pad_gpio_port0_z[09])
);
PAD_INOUT8MA_NOE uPAD_P0_10 (
.PAD (P0[10]),
.O (pad_gpio_port0_o[10]),
.I (pad_gpio_port0_i[10]),
.NOE (pad_gpio_port0_z[10])
);
PAD_INOUT8MA_NOE uPAD_P0_11 (
.PAD (P0[11]),
.O (pad_gpio_port0_o[11]),
.I (pad_gpio_port0_i[11]),
.NOE (pad_gpio_port0_z[11])
);
PAD_INOUT8MA_NOE uPAD_P0_12 (
.PAD (P0[12]),
.O (pad_gpio_port0_o[12]),
.I (pad_gpio_port0_i[12]),
.NOE (pad_gpio_port0_z[12])
);
PAD_INOUT8MA_NOE uPAD_P0_13 (
.PAD (P0[13]),
.O (pad_gpio_port0_o[13]),
.I (pad_gpio_port0_i[13]),
.NOE (pad_gpio_port0_z[13])
);
PAD_INOUT8MA_NOE uPAD_P0_14 (
.PAD (P0[14]),
.O (pad_gpio_port0_o[14]),
.I (pad_gpio_port0_i[14]),
.NOE (pad_gpio_port0_z[14])
);
PAD_INOUT8MA_NOE uPAD_P0_15 (
.PAD (P0[15]),
.O (pad_gpio_port0_o[15]),
.I (pad_gpio_port0_i[15]),
.NOE (pad_gpio_port0_z[15])
);
// GPI.I Port 1 x 16
PAD_INOUT8MA_NOE uPAD_P1_00 (
.PAD (P1[00]),
.O (pad_gpio_port1_o[00]),
.I (pad_gpio_port1_i[00]),
.NOE (pad_gpio_port1_z[00])
);
PAD_INOUT8MA_NOE uPAD_P1_01 (
.PAD (P1[01]),
.O (pad_gpio_port1_o[01]),
.I (pad_gpio_port1_i[01]),
.NOE (pad_gpio_port1_z[01])
);
PAD_INOUT8MA_NOE uPAD_P1_02 (
.PAD (P1[02]),
.O (pad_gpio_port1_o[02]),
.I (pad_gpio_port1_i[02]),
.NOE (pad_gpio_port1_z[02])
);
PAD_INOUT8MA_NOE uPAD_P1_03 (
.PAD (P1[03]),
.O (pad_gpio_port1_o[03]),
.I (pad_gpio_port1_i[03]),
.NOE (pad_gpio_port1_z[03])
);
PAD_INOUT8MA_NOE uPAD_P1_04 (
.PAD (P1[04]),
.O (pad_gpio_port1_o[04]),
.I (pad_gpio_port1_i[04]),
.NOE (pad_gpio_port1_z[04])
);
PAD_INOUT8MA_NOE uPAD_P1_05 (
.PAD (P1[05]),
.O (pad_gpio_port1_o[05]),
.I (pad_gpio_port1_i[05]),
.NOE (pad_gpio_port1_z[05])
);
PAD_INOUT8MA_NOE uPAD_P1_06 (
.PAD (P1[06]),
.O (pad_gpio_port1_o[06]),
.I (pad_gpio_port1_i[06]),
.NOE (pad_gpio_port1_z[06])
);
PAD_INOUT8MA_NOE uPAD_P1_07 (
.PAD (P1[07]),
.O (pad_gpio_port1_o[07]),
.I (pad_gpio_port1_i[07]),
.NOE (pad_gpio_port1_z[07])
);
PAD_INOUT8MA_NOE uPAD_P1_08 (
.PAD (P1[08]),
.O (pad_gpio_port1_o[08]),
.I (pad_gpio_port1_i[08]),
.NOE (pad_gpio_port1_z[08])
);
PAD_INOUT8MA_NOE uPAD_P1_09 (
.PAD (P1[09]),
.O (pad_gpio_port1_o[09]),
.I (pad_gpio_port1_i[09]),
.NOE (pad_gpio_port1_z[09])
);
PAD_INOUT8MA_NOE uPAD_P1_10 (
.PAD (P1[10]),
.O (pad_gpio_port1_o[10]),
.I (pad_gpio_port1_i[10]),
.NOE (pad_gpio_port1_z[10])
);
PAD_INOUT8MA_NOE uPAD_P1_11 (
.PAD (P1[11]),
.O (pad_gpio_port1_o[11]),
.I (pad_gpio_port1_i[11]),
.NOE (pad_gpio_port1_z[11])
);
PAD_INOUT8MA_NOE uPAD_P1_12 (
.PAD (P1[12]),
.O (pad_gpio_port1_o[12]),
.I (pad_gpio_port1_i[12]),
.NOE (pad_gpio_port1_z[12])
);
PAD_INOUT8MA_NOE uPAD_P1_13 (
.PAD (P1[13]),
.O (pad_gpio_port1_o[13]),
.I (pad_gpio_port1_i[13]),
.NOE (pad_gpio_port1_z[13])
);
PAD_INOUT8MA_NOE uPAD_P1_14 (
.PAD (P1[14]),
.O (pad_gpio_port1_o[14]),
.I (pad_gpio_port1_i[14]),
.NOE (pad_gpio_port1_z[14])
);
PAD_INOUT8MA_NOE uPAD_P1_15 (
.PAD (P1[15]),
.O (pad_gpio_port1_o[15]),
.I (pad_gpio_port1_i[15]),
.NOE (pad_gpio_port1_z[15])
);
endmodule
flist/nanosoc_ASIC.flist
View file @ 02f873a7
......@@ -22,6 +22,10 @@
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
......
flist/nanosoc_FPGA.flist 0 → 100644
View file @ 02f873a7
//-----------------------------------------------------------------------------
// NanoSoC Top-level Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC IP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC IP search path =============
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
// Include Corstone IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_ip.flist
// SLCore Files
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0.flist
// Debug IP
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
// DMAC IP (better included at top level configuration)
//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
//-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
flows/makefile.fpga
View file @ 02f873a7
......@@ -68,7 +68,7 @@ code:
flist_tcl_nanosoc: gen_defs
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC_FPGA) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
# Package NanoSoC Socket Components
package_socket:
......
fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
View file @ 02f873a7
......@@ -20,15 +20,15 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
# set scripts_vivado_version 2021.1
# set current_vivado_version [version -short]
#
# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# puts ""
# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
#
# return 1
# }
################################################################
# START
......
fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
View file @ 02f873a7
......@@ -20,15 +20,15 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
# set scripts_vivado_version 2021.1
# set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# puts ""
# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
# return 1
# }
################################################################
# START
......@@ -46,7 +46,7 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
soclabs.org:user:nanosoc_chip:1.0\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:zynq_ultra_ps_e:3.3\
xilinx.com:ip:zynq_ultra_ps_e:3.5\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
......@@ -373,7 +373,7 @@ proc create_root_design { parentCell } {
] $xlconstant_zerox4
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
set_property -dict [ list \
CONFIG.CAN0_BOARD_INTERFACE {custom} \
CONFIG.CAN1_BOARD_INTERFACE {custom} \
......
makefile
View file @ 02f873a7
......@@ -185,6 +185,7 @@ else
endif
endif
DESIGN_VC_FPGA ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist
# Make variables visible to target shells
export ARM_CORTEX_M0_DIR
export ARM_CORSTONE_101_DIR
......