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.gitignore
View file @ 02f873a7
......@@ -10,24 +10,43 @@ ASIC/*.mr
ASIC/*.pvk
ASIC/alib-52
ASIC/WORK/*
ASIC/*/Cadence/scripts/fv
ASIC/*/Cadence/scripts/*.rpt
ASIC/*/Cadence/scripts/*.tstamp
ASIC/*/Cadence/scripts/.cadence
ASIC/*/Cadence/scripts/.*
ASIC/*/Cadence/scripts/*.spec
ASIC/*/Cadence/scripts/*.sdf
ASIC/*/Cadence/scripts/*.gif
ASIC/*/Cadence/scripts/*.lef
ASIC/*/Cadence/scripts/result
ASIC/*/Cadence/scripts/nanosoc_chip_pads
ASIC/*/Cadence/scripts/timingReports
ASIC/*/Cadence/scripts/*.db*
ASIC/*/Cadence/scripts/*.rpt*
ASIC/*/Cadence/scripts/*.checkFPlan
ASIC/*/Cadence/scripts/*.ptiavg
ASIC/*/Cadence/scripts/*.ptifiles
ASIC/*/*/Cadence/scripts/fv
ASIC/*/*/Cadence/scripts/*.rpt
ASIC/*/*/Cadence/scripts/*.tstamp
ASIC/*/*/Cadence/scripts/.cadence
ASIC/*/*/Cadence/scripts/.*
ASIC/*/*/Cadence/scripts/*.spec
ASIC/*/*/Cadence/scripts/*.sdf
ASIC/*/*/Cadence/scripts/*.gif
ASIC/*/*/Cadence/scripts/*.lef
ASIC/*/*/Cadence/scripts/result
ASIC/*/*/Cadence/scripts/nanosoc_chip_pads
ASIC/*/*/Cadence/scripts/timingReports
ASIC/*/*/Cadence/scripts/*.db*
ASIC/*/*/Cadence/scripts/*.rpt*
ASIC/*/*/Cadence/scripts/*.checkFPlan
ASIC/*/*/Cadence/scripts/*.ptiavg
ASIC/*/*/Cadence/scripts/*.ptifiles
ASIC/*/*/Cadence/scripts/*.dofile
ASIC/*/*/Cadence/scripts/*.testproc
ASIC/*/*/Cadence/scripts/scheduling_file.cts.*
ASIC/*/*/Synopsys_FC/HDL_LIBRARIES
ASIC/*/*/Synopsys_FC/nanosoc_chip_pads.dlib
ASIC/*/*/Synopsys_FC/*.txt
ASIC/*/*/Synopsys_FC/fc_output.txt
ASIC/*/*/Synopsys_FC/*.log
ASIC/*/*/Synopsys_FC/check_design.ems
ASIC/*/*/Synopsys_FC/PreFrameCheck
ASIC/*/*/Synopsys_FC/*.svf
ASIC/*/*/Synopsys_FC/rom_via
ASIC/*/*/Synopsys_FC/sram_16k
ASIC/*/*/Synopsys_FC/pad_lib
ASIC/*/*/Synopsys_FC/.*/
ASIC/*/*/Synopsys_FC/cln28ht
ASIC/*/*/Synopsys_FC/cln28ht_pmk
ASIC/*/*/Synopsys_FC/cln28ht_ret
ASIC/*/*/Synopsys_FC/io_lib
ASIC/*/*/Synopsys_FC/legalizer_debug_plots
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
......@@ -35,6 +54,15 @@ ASIC/Synopsys/ICC2/tsmc65lp/*
ASIC/Synopsys/ICC2/*.svf
ASIC/Synopsys/ICC2/*.ems
ASIC/Synopsys/ICC2/icc2_output.txt
ASIC/TSMC28nm/no_pins/Synopsys_FC/cln28ht
ASIC/TSMC28nm/no_pins/Synopsys_FC/rom_via
ASIC/TSMC28nm/no_pins/Synopsys_FC/PreFrameCheck
ASIC/TSMC28nm/no_pins/Synopsys_FC/sram_16k
ASIC/TSMC28nm/no_pins/Synopsys_FC/*.svf
ASIC/TSMC28nm/no_pins/Synopsys_FC/*.txt
ASIC/TSMC28nm/no_pins/Synopsys_FC/*.log
ASIC/TSMC28nm/no_pins/Synopsys_FC/.*
*.pvl
*.syn
*.mr
......
ASIC/TSMC28nm/38pin/Synopsys_FC/FC_flow.tcl 0 → 100644
View file @ 02f873a7
# Main flow for Synopsys fusion compiler
set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
# Design setup: read libraries and RTL
redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
# Floorplan setup
redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1111.1111111 1111.11111} -core_offset {140}}
redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
place_io
# Read Constraints
redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../../constraints.sdc}
# Power Plan
load_upf nanosoc_chip_pads.upf
create_voltage_area -power_domains ACCEL
create_voltage_area -power_domains PD_DBG
create_voltage_area -power_domains PD_SYS
create_voltage_area_shape -voltage_area ACCEL \
-region {{{140.000 140.000} {370.655 311.165}}} \
-guard_band {2 2}
create_voltage_area_shape -voltage_area PD_DBG \
-region {{{703.115 140.000} {971.040 329.520}}} \
-guard_band {2 2}
create_voltage_area_shape -voltage_area PD_SYS \
-region {{{234.000 453.940} {548.100 645.665}}} \
-guard_band {2 2}
create_pg_region {pg_accel} -voltage_area {ACCEL}
create_pg_region {pg_dbg} -voltage_area {PD_DBG}
create_pg_region {pg_sys} -voltage_area {PD_SYS}
redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
# Init coarse placement
redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
# Physical aware synthesis
redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
save_lib nanosoc_chip_pads.dlib
redirect -tee -file $LOG_DIR/08_clock_tree.log {synthesize_clock_trees -clocks {clk swdclk}}
redirect -tee -file $LOG_DIR/09_clock_opt.log {clock_opt}
redirect -tee -file $REPORT_DIR/timing_02_clock_opt.rep {report_timing}
ASIC/TSMC28nm/38pin/Synopsys_FC/design_setup.tcl 0 → 100644
View file @ 02f873a7
set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
set TLU_cbest $TLU_dir/cbest.tluplus
set TLU_cworst $TLU_dir/cworst.tluplus
set TLU_rcbest $TLU_dir/rcbest.tluplus
set TLU_rcworst $TLU_dir/rcworst.tluplus
set TLU_map $TLU_dir/tluplus.map
create_lib nanosoc_chip_pads.dlib \
-technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
-ref_libs {./cln28ht/ ./cln28ht_pmk/ ./cln28ht_ret/ ./sram_16k/ ./rom_via/ ./io_lib/ ./pad_lib/}
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
elaborate nanosoc_chip_pads
set_top_module nanosoc_chip_pads
redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
redirect -tee -file ./lib_cell_pmk_summary.log {report_lib -cell_summary cln28ht_pmk}
redirect -tee -file ./lib_cell_ret_summary.log {report_lib -cell_summary cln28ht_ret}
read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
save_lib nanosoc_chip_pads.dlib
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def 0 → 100644
View file @ 02f873a7
#
# Fusion Compiler write_def
# Release : U-2022.12
# User Name : dwn1c21
# Date : Fri Oct 25 13:42:48 2024
#
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN nanosoc_chip_pads ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 0 1110700 ) ( 1111040 1110700 ) ( 1111040 0 ) ;
END DESIGN
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
#
################################################################################
set _dirName__0 [file dirname [file normalize [info script]]]
source ${_dirName__0}/fp.tcl
if { [get_attribute -name view_name [current_block]] == "design" } {
set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
if { [string length ${__fp_crnt_label_name__} ] != 0 } {
set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
} else {
set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
}
if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
if { [get_attribute -name has_editable_abstract [current_block]] } {
echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract
save_lib -all
} else {
echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract -placement
save_lib -all
}
} elseif { ${__fp_crnt_abs_type__} == "placement" } {
echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract -placement
save_lib -all
} else {
echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract
save_lib -all
}
}
}
}
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc compare_floorplans on Fri Oct 25 13:42:48 2024
#
# DO NOT EDIT - automatically generated file
#
################################################################################
START nanosoc_chip_pads
MACROS
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {140.0000 919.4450} {304.6650 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {626.6800 781.1650} {798.8600 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {798.8600 781.1650} {971.0400 970.7000} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {798.8600 563.3200} {971.0400 752.8550} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {626.6800 563.3200} {798.8600 752.8550} }
PINS
VDDIO { {555.5200 555.3500} {555.5201 555.3501} }
VSSIO { {555.5200 555.3500} {555.5201 555.3501} }
VDD { {555.5200 555.3500} {555.5201 555.3501} }
VSS { {555.5200 555.3500} {555.5201 555.3501} }
VDDACC { {555.5200 555.3500} {555.5201 555.3501} }
SE { {555.5200 555.3500} {555.5201 555.3501} }
CLK { {555.5200 555.3500} {555.5201 555.3501} }
TEST { {555.5200 555.3500} {555.5201 555.3501} }
NRST { {555.5200 555.3500} {555.5201 555.3501} }
P0[7] { {555.5200 555.3500} {555.5201 555.3501} }
P0[6] { {555.5200 555.3500} {555.5201 555.3501} }
P0[5] { {555.5200 555.3500} {555.5201 555.3501} }
P0[4] { {555.5200 555.3500} {555.5201 555.3501} }
P0[3] { {555.5200 555.3500} {555.5201 555.3501} }
P0[2] { {555.5200 555.3500} {555.5201 555.3501} }
P0[1] { {555.5200 555.3500} {555.5201 555.3501} }
P0[0] { {555.5200 555.3500} {555.5201 555.3501} }
P1[7] { {555.5200 555.3500} {555.5201 555.3501} }
P1[6] { {555.5200 555.3500} {555.5201 555.3501} }
P1[5] { {555.5200 555.3500} {555.5201 555.3501} }
P1[4] { {555.5200 555.3500} {555.5201 555.3501} }
P1[3] { {555.5200 555.3500} {555.5201 555.3501} }
P1[2] { {555.5200 555.3500} {555.5201 555.3501} }
P1[1] { {555.5200 555.3500} {555.5201 555.3501} }
P1[0] { {555.5200 555.3500} {555.5201 555.3501} }
SWDIO { {555.5200 555.3500} {555.5201 555.3501} }
SWDCK { {555.5200 555.3500} {555.5201 555.3501} }
END nanosoc_chip_pads
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
#
################################################################################
set _dirName__0 [file dirname [file normalize [info script]]]
################################################################################
# Read DEF
################################################################################
read_def ${_dirName__0}/floorplan.def
################################################################################
# Macros
################################################################################
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R0
set_attribute -quiet -objects $cellInst -name origin -value { 140.0000 919.4450 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 563.3200 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 563.3200 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
################################################################################
# User attributes of macros
################################################################################
################################################################################
# Bounds and user attributes of bound shapes
################################################################################
remove_bounds -all
################################################################################
# User attributes of bounds
################################################################################
################################################################################
# Blockages
################################################################################
remove_routing_blockages -all -force
remove_placement_blockages -all -force
remove_pin_blockages -all
remove_shaping_blockages -all
################################################################################
# User attributes of blockages
################################################################################
################################################################################
# Module Boundaries
################################################################################
set hbCells [get_cells -quiet -filter hierarchy_type==boundary -hierarchical]
if [sizeof_collection $hbCells] {
set_cell_hierarchy_type -type normal $hbCells
}
################################################################################
# I/O guides
################################################################################
remove_io_guides -all
create_io_guide -name main_io_ring.left -side left -line { {0.0000 110.0000} \
890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_CLK_I uPAD_NRST_I \
uPAD_P0_00 uPAD_P0_01 uPAD_P0_02 uPAD_P0_03 uPAD_P0_04 uPAD_P0_05 uPAD_P0_06 }
create_io_guide -name main_io_ring.bottom -side bottom -line { {1001.0400 \
0.0000} 891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_P0_07 \
uPAD_P1_00 uPAD_P1_01 uPAD_P1_02 uPAD_P1_03 uPAD_P1_04 uPAD_P1_05 \
uPAD_P1_06 uPAD_P1_07 uPAD_SE_I }
create_io_guide -name main_io_ring.right -side right -line { {1111.0400 \
1000.7000} 890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_SWDCK_I \
uPAD_SWDIO_IO uPAD_TEST_I uPAD_VDDACC_0 uPAD_VDDACC_1 uPAD_VDDACC_2 \
uPAD_VDDIO_0 uPAD_VDDIO_2 uPAD_VDDIO_3 }
create_io_guide -name main_io_ring.top -side top -line { {110.0000 1110.7000} \
891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_VDD_0 uPAD_VDD_1 \
uPAD_VDD_2 uPAD_VDD_3 uPAD_VSSIO_0 uPAD_VSSIO_1 uPAD_VSS_0 uPAD_VSS_1 \
uPAD_VSS_2 uPAD_VSS_3 }
################################################################################
# User attributes of I/O guides
################################################################################
################################################################################
# User attributes of current block
################################################################################
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/mapfile 0 → 100644
View file @ 02f873a7
nanosoc_chip_pads FLOORPLAN fp.tcl
ASIC/TSMC28nm/38pin/Synopsys_FC/init_placement.tcl 0 → 100644
View file @ 02f873a7
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
set_temperature -40 -min 125 -corners default
set_voltage 0.81 -min 0.99 -corners default
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_SYS}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_DBG}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDDACC}] 0.81
set_voltage -min 0.0 -corners default -object_list [get_supply_nets {VSS}] 0.0
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
explore_logic_hierarchy -place -rectangular
save_lib nanosoc_chip_pads.dlib
ASIC/TSMC28nm/38pin/Synopsys_FC/nanosoc_chip_pads.upf 0 → 100644
View file @ 02f873a7
################################################################################
# Create power domains
################################################################################
create_power_domain TOP
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
create_power_domain PD_SYS -elements u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys
create_power_domain PD_DBG -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_dbg \
u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_dap/u_ap}
################################################################################
# Create and logically connect power ports and nets
################################################################################
# Always on VDD
create_supply_port VDD
create_supply_net VDD -domain TOP
create_supply_net VDD -domain PD_SYS -reuse
create_supply_net VDD -domain PD_DBG -reuse
connect_supply_net VDD -ports VDD
# Ground
create_supply_port VSS
create_supply_net VSS -domain TOP
create_supply_net VSS -domain PD_SYS -reuse
create_supply_net VSS -domain PD_DBG -reuse
create_supply_net VSS -domain ACCEL -reuse
connect_supply_net VSS -ports VSS
# Switched VDD
create_supply_net VDD_SYS -domain PD_SYS -resolve parallel
create_supply_net VDD_DBG -domain PD_DBG -resolve parallel
# VDDACC
create_supply_port VDDACC
create_supply_net VDDACC -domain ACCEL
connect_supply_net VDDACC -ports VDDACC
################################################################################
# Assign power supplies to power domains
################################################################################
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
set_domain_supply_net PD_SYS -primary_power_net VDD_SYS -primary_ground_net VSS
set_domain_supply_net PD_DBG -primary_power_net VDD_DBG -primary_ground_net VSS
################################################################################
# Create Power Switches
################################################################################
create_power_switch uswitch1 -domain PD_SYS \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_SYS VDD_SYS} \
-control_port {SYSPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWN} \
-ack_port {SYSPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWNACK {SYSPWRDOWN}} \
-ack_delay {SYSPWRDOWNACK 65000} \
-on_state {on_state VDD {!SYSPWRDOWN}} \
-off_state {off_state { SYSPWRDOWN}}
create_power_switch uswitch2 -domain PD_DBG \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_DBG VDD_DBG} \
-control_port {DBGPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWN} \
-ack_port {DBGPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWNACK {DBGPWRDOWN}} \
-ack_delay {DBGPWRDOWNACK 65000} \
-on_state {on_state VDD {!DBGPWRDOWN}} \
-off_state {off_state { DBGPWRDOWN}}
################################################################################
# Set Isolation Controls
# - iso_low1, iso_high1 at PD_SYS outputs
# - iso_low2 at PD_DBG outputs
################################################################################
set_isolation iso_low1 -domain PD_SYS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
# The signals that need to be clamped HIGH
set_isolation iso_high1 -domain PD_SYS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 1 \
-elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleeping_o \
u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleep_deep_o}
set_isolation_control iso_low1 -domain PD_SYS \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
-isolation_sense low \
-location parent
set_isolation_control iso_high1 -domain PD_SYS \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
-isolation_sense low \
-location parent
set_isolation iso_low2 -domain PD_DBG \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
set_isolation_control iso_low2 -domain PD_DBG \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGISOLATEn \
-isolation_sense low \
-location parent
################################################################################
# Set Retention
################################################################################
set_retention drff -domain PD_SYS -retention_power_net VDD -retention_ground_net VSS
set_retention_control drff -domain PD_SYS -save_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn high} \
-restore_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn low}
map_retention_cell drff -domain PD_SYS -lib_cell_type DRFF
################################################################################
# Define port states
################################################################################
add_port_state VSS -state {on 0.0 0.0 0.0}
add_port_state VDD -state {on 0.81 0.9 0.99}
add_port_state VDDACC -state {on 0.81 0.9 0.99}
add_port_state uswitch1/VDD_SYS -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
add_port_state uswitch2/VDD_DBG -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
################################################################################
# Define power state table
################################################################################
create_pst cm0_pst -supplies {VSS VDD VDD_SYS VDD_DBG VDDACC}
add_pst_state run -pst cm0_pst -state {on on on off on }
add_pst_state slp -pst cm0_pst -state {on on off off on }
add_pst_state dbg -pst cm0_pst -state {on on on on on }
ASIC/TSMC28nm/38pin/Synopsys_FC/power_plan.tcl 0 → 100644
View file @ 02f873a7
connect_pg_net -create_nets_only
connect_pg_net -automatic
create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
-vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VDDACC VSS}} {offset: {3 3}}} -core
compile_pg -strategies core_ring
create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
{{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VDDACC VSS}}} -core
compile_pg -strategies M5M8_mesh
create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
set_pg_strategy std_cell_accel -voltage_areas ACCEL -pattern {{name : std_pattern}{nets : {VDDACC VSS}}}
set_pg_strategy std_cell_dbg -voltage_areas PD_DBG -pattern {{name : std_pattern}{nets : {VDD_DBG VSS}}}
set_pg_strategy std_cell_sys -voltage_areas PD_SYS -pattern {{name : std_pattern}{nets : {VDD_SYS VSS}}}
set_pg_strategy std_cell_strat -voltage_areas DEFAULT_VA -pattern {{name: std_pattern} {nets: {VDD VSS}}}
compile_pg -strategies std_cell_accel
compile_pg -strategies std_cell_dbg
compile_pg -strategies std_cell_sys
compile_pg -strategies std_cell_strat
ASIC/TSMC28nm/38pin/Synopsys_FC/synopsys_lib_conversion.tcl 0 → 100644
View file @ 02f873a7
## Paths Please Edit for your system
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set pmk_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0
set ret_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_rklo_lvt_svt_c30_c35/r1p0
# Technology files
set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf
set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
# Standard Cell libraries
set standard_cell_lef_file $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
set standard_cell_gds_file $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
set standard_cell_db_file_ss_0p81v_125C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
set standard_cell_db_file_tt_0p90v_25C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
set standard_cell_db_file_ff_0p99v_m40C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
set standard_cell_antenna_file $standard_cell_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_base_svt_c35_antenna.clf
# Power Management Kit
set pmk_lef_file $pmk_base_path/lef/sc12mcpp140z_cln28ht_pmk_svt_c35.lef
set pmk_gds_file $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
set pmk_db_file_ss_0p81v_125C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_125c.db
set pmk_db_file_tt_0p90v_25C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_25c.db
set pmk_db_file_ff_0p99v_m40C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c.db
set pmk_antenna_file $pmk_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_pmk_svt_c35_antenna.clf
# Retention Kit
set ret_lef_file $ret_base_path/lef/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.lef
set ret_gds_file $ret_base_path/gds2/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.gds2
set ret_db_file_ss_0p81v_125C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_125c.db
set ret_db_file_tt_0p90v_25C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_25c.db
set ret_db_file_ff_0p99v_m40C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_m40c.db
set ret_antenna_file $ret_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_antenna.clf
# IO Paths
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set tphn28hpcpgv18_lef_file $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/6lm/lef/tphn28hpcpgv18_6lm.lef
set tphn28hpcpgv18_lib_path $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set IO_TT_0p9v_1p8v_25c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18tt0p9v1p8v25c.db
set IO_FF_0p99v_1p98v_m40c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ffg0p99v1p98vm40c.db
set IO_SS_0p81v_1p62v_125c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ssg0p81v1p62v125c.db
set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
# SRAM files (using Arm compiler)
set sram_16k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
set sram_16k_lef_file $sram_16k_path/sram_16k.lef
set sram_16k_gds_file $sram_16k_path/sram_16k.gds2
set sram_16k_lib_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
set sram_16k_lib_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_16k_db_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
set sram_16k_db_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
# ROM Files (using arm Compiler)
set rom_path $env(SOCLABS_PROJECT_DIR)/memories/bootrom
set rom_via_lef_file $rom_path/rom_via.lef
set rom_via_gds_file $rom_path/rom_via.gds2
set rom_via_lib_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
set rom_via_lib_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
set rom_via_lib_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
set rom_via_db_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
set rom_via_db_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
set rom_via_db_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
# Create standard cell fusion library
create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p81v_125C $standard_cell_db_file_tt_0p90v_25C $standard_cell_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
save_fusion_lib cln28ht
close_fusion_lib cln28ht
# Create Power Management Kit fusion library
create_fusion_lib -dbs [list $pmk_db_file_ss_0p81v_125C $pmk_db_file_tt_0p90v_25C $pmk_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $pmk_lef_file] -technology $cln28ht_tech_file cln28ht_pmk
save_fusion_lib cln28ht_pmk
close_fusion_lib cln28ht_pmk
# Create Retention fusion library
create_fusion_lib -dbs [list $ret_db_file_ss_0p81v_125C $ret_db_file_tt_0p90v_25C $ret_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $ret_lef_file] -technology $cln28ht_tech_file cln28ht_ret
save_fusion_lib cln28ht_ret
close_fusion_lib cln28ht_ret
# 16K SRAM
read_lib $sram_16k_lib_file_ss_0p81v_125c
write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
read_lib $sram_16k_lib_file_tt_0p90v_25c
write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
close_lib -all
read_lib $sram_16k_lib_file_ff_0p99v_m40c
write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
save_fusion_lib sram_16k
close_fusion_lib sram_16k
# Boot ROM
read_lib $rom_via_lib_file_ss_0p81v_125c
write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
read_lib $rom_via_lib_file_tt_0p90v_25c
write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
close_lib -all
read_lib $rom_via_lib_file_ff_0p99v_m40c
write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $rom_via_db_file_ss_0p81v_125c $rom_via_db_file_tt_0p90v_25c $rom_via_db_file_ff_0p99v_m40c] -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
save_fusion_lib rom_via
close_fusion_lib rom_via
# IO Lib
create_fusion_lib -dbs [list $IO_SS_0p81v_1p62v_125c_db $IO_TT_0p9v_1p8v_25c_db $IO_FF_0p99v_1p98v_m40c_db] -lefs $tphn28hpcpgv18_lef_file -technology $cln28ht_tech_file io_lib
save_fusion_lib io_lib
close_fusion_lib io_lib
# Pad Lib
create_fusion_lib -lefs $pad_lef_file -technology $cln28ht_tech_file pad_lib
save_fusion_lib pad_lib
close_fusion_lib pad_lib
exit
\ No newline at end of file
ASIC/TSMC28nm/constraints.sdc 0 → 100644
View file @ 02f873a7
#-----------------------------------------------------------------------------
# NanoSoC Constraints for Synthesis
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#### CLOCK DEFINITION
set EXTCLK "clk";
set SWDCLK "swdclk";
set_units -time ns;
set_units -capacitance pF;
set EXTCLK_PERIOD 4.16667;
set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
set INTER_CLOCK_UNCERTAINTY 0.1
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $SWDCLK] -rise_to [get_clocks $EXTCLK]
set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $EXTCLK] -rise_to [get_clocks $SWDCLK]
### Multicycle path through asynchronous clock domains
set_multicycle_path 2 -setup -end -from SWDCK -to CLK
set_multicycle_path 1 -hold -end -from SWDCK -to CLK
set_multicycle_path 2 -setup -end -from CLK -to SWDCK
set_multicycle_path 1 -hold -end -from CLK -to SWDCK
set_false_path -hold -from CLK -to SWDCK
### Multicycle path through pads
set_false_path -through uPAD_SWDIO_IO
set_multicycle_path 2 -through uPAD_SWDIO_IO
#set_false_path -through uPAD_P0_*
#set_false_path -through uPAD_P1_*
set_multicycle_path 2 -from uPAD_SWDIO_IO/I -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/IE -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/DS -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/OEN -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_P0_*/I -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/IE -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/DS -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/OEN -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P1_*/I -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/IE -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/DS -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/OEN -to uPAD_P1_*/C
#### DELAY DEFINITION
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports NRST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports TEST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P1]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.1 [get_ports SWDIO]
set_max_capacitance 3 [all_outputs]
set_max_fanout 10 [all_inputs]
ASIC/TSMC28nm/no_pins/Synopsys_FC/FC_flow.tcl 0 → 100644
View file @ 02f873a7
# Main flow for Synopsys fusion compiler
set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
# Design setup: read libraries and RTL
redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
# Floorplan setup
redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1111.1111111 1111.11111} -core_offset {140}}
redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
# Read Constraints
redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../../constraints.sdc}
# Power Plan
redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
# Init coarse placement
redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
# Physical aware synthesis
redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
save_lib nanosoc_chip_pads.dlib
redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl
View file @ 02f873a7
set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
set TLU_cbest $TLU_dir/cbest.tluplus
set TLU_cworst $TLU_dir/cworst.tluplus
set TLU_rcbest $TLU_dir/rcbest.tluplus
set TLU_rcworst $TLU_dir/rcworst.tluplus
set TLU_map $TLU_dir/tluplus.map
create_lib nanosoc_chip_pads.dlib \
-technology $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf \
-ref_libs {./cln28ht_sc9mcpp140z/}
-technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf \
-ref_libs {./cln28ht/ ./sram_16k/ ./rom_via/}
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
analyze -format verilog $env(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_no_pads.v
elaborate nanosoc_chip_pads
set_top_module nanosoc_chip_pads
\ No newline at end of file
set_top_module nanosoc_chip_pads
redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
save_lib nanosoc_chip_pads.dlib
ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.def 0 → 100644
View file @ 02f873a7
#
# Fusion Compiler write_def
# Release : U-2022.12
# User Name : dwn1c21
# Date : Thu Sep 12 11:29:50 2024
#
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN nanosoc_chip_pads ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 0 1110700 ) ( 1111040 1110700 ) ( 1111040 0 ) ;
END DESIGN
ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan.tcl 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc write_floorplan on Thu Sep 12 11:29:50 2024
#
################################################################################
set _dirName__0 [file dirname [file normalize [info script]]]
source ${_dirName__0}/fp.tcl
if { [get_attribute -name view_name [current_block]] == "design" } {
set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
if { [string length ${__fp_crnt_label_name__} ] != 0 } {
set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
} else {
set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
}
if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
if { [get_attribute -name has_editable_abstract [current_block]] } {
echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract
save_lib -all
} else {
echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract -placement
save_lib -all
}
} elseif { ${__fp_crnt_abs_type__} == "placement" } {
echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract -placement
save_lib -all
} else {
echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
create_abstract
save_lib -all
}
}
}
}
ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/floorplan_compare_data.txt 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc compare_floorplans on Thu Sep 12 11:29:50 2024
#
# DO NOT EDIT - automatically generated file
#
################################################################################
START nanosoc_chip_pads
MACROS
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {140.0000 944.1350} {235.0500 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {282.3200 781.1650} {454.5000 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {454.5000 781.1650} {626.6800 970.7000} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {798.8600 781.1650} {971.0400 970.7000} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {626.6800 781.1650} {798.8600 970.7000} }
PINS
SE { {555.5200 555.3500} {555.5201 555.3501} }
CLK { {555.5200 555.3500} {555.5201 555.3501} }
TEST { {555.5200 555.3500} {555.5201 555.3501} }
NRST { {555.5200 555.3500} {555.5201 555.3501} }
P0[15] { {555.5200 555.3500} {555.5201 555.3501} }
P0[14] { {555.5200 555.3500} {555.5201 555.3501} }
P0[13] { {555.5200 555.3500} {555.5201 555.3501} }
P0[12] { {555.5200 555.3500} {555.5201 555.3501} }
P0[11] { {555.5200 555.3500} {555.5201 555.3501} }
P0[10] { {555.5200 555.3500} {555.5201 555.3501} }
P0[9] { {555.5200 555.3500} {555.5201 555.3501} }
P0[8] { {555.5200 555.3500} {555.5201 555.3501} }
P0[7] { {555.5200 555.3500} {555.5201 555.3501} }
P0[6] { {555.5200 555.3500} {555.5201 555.3501} }
P0[5] { {555.5200 555.3500} {555.5201 555.3501} }
P0[4] { {555.5200 555.3500} {555.5201 555.3501} }
P0[3] { {555.5200 555.3500} {555.5201 555.3501} }
P0[2] { {555.5200 555.3500} {555.5201 555.3501} }
P0[1] { {555.5200 555.3500} {555.5201 555.3501} }
P0[0] { {555.5200 555.3500} {555.5201 555.3501} }
P1[15] { {555.5200 555.3500} {555.5201 555.3501} }
P1[14] { {555.5200 555.3500} {555.5201 555.3501} }
P1[13] { {555.5200 555.3500} {555.5201 555.3501} }
P1[12] { {555.5200 555.3500} {555.5201 555.3501} }
P1[11] { {555.5200 555.3500} {555.5201 555.3501} }
P1[10] { {555.5200 555.3500} {555.5201 555.3501} }
P1[9] { {555.5200 555.3500} {555.5201 555.3501} }
P1[8] { {555.5200 555.3500} {555.5201 555.3501} }
P1[7] { {555.5200 555.3500} {555.5201 555.3501} }
P1[6] { {555.5200 555.3500} {555.5201 555.3501} }
P1[5] { {555.5200 555.3500} {555.5201 555.3501} }
P1[4] { {555.5200 555.3500} {555.5201 555.3501} }
P1[3] { {555.5200 555.3500} {555.5201 555.3501} }
P1[2] { {555.5200 555.3500} {555.5201 555.3501} }
P1[1] { {555.5200 555.3500} {555.5201 555.3501} }
P1[0] { {555.5200 555.3500} {555.5201 555.3501} }
SWDIO { {555.5200 555.3500} {555.5201 555.3501} }
SWDCK { {555.5200 555.3500} {555.5201 555.3501} }
END nanosoc_chip_pads
ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/fp.tcl 0 → 100644
View file @ 02f873a7
################################################################################
#
# Created by fc write_floorplan on Thu Sep 12 11:29:50 2024
#
################################################################################
set _dirName__0 [file dirname [file normalize [info script]]]
################################################################################
# Read DEF
################################################################################
read_def ${_dirName__0}/floorplan.def
################################################################################
# Macros
################################################################################
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 235.0500 944.1350 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 454.5000 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 626.6800 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 781.1650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
################################################################################
# User attributes of macros
################################################################################
################################################################################
# I/O guides
################################################################################
remove_io_guides -all
################################################################################
# User attributes of I/O guides
################################################################################
################################################################################
# User attributes of current block
################################################################################
ASIC/TSMC28nm/no_pins/Synopsys_FC/floorplan/mapfile 0 → 100644
View file @ 02f873a7
nanosoc_chip_pads FLOORPLAN fp.tcl