verif/tb/verilog/nanosoc_tb_qs.v

@@ -113,6 +113,7 @@ SROM_Ax32
   .VSS        (VSS),
   .VDDACC     (VDDACC),
 `endif
+  .SE         (1'b0),
   .CLK        (CLK),  // input
   .TEST       (TEST),  // output
   .NRST       (NRST),   // active low reset
@@ -337,6 +338,7 @@ reg baud_clk_del;
   ) u_nanosoc_axi_stream_io_8_rxd_to_file (
     .aclk         (CLK),
     .aresetn      (NRST),
+    .eof_received ( ),
     .rxd8_ready   (rxd8_tready),
     .rxd8_valid   (rxd8_tvalid),
     .rxd8_data    (rxd8_tdata)

verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v

@@ -21,6 +21,7 @@ module nanosoc_axi_stream_io_8_rxd_to_file
   (
   input  wire       aclk,
   input  wire       aresetn,
+  output wire       eof_received,
   output wire       rxd8_ready,
   input  wire       rxd8_valid,
   input  wire [7:0] rxd8_data
@@ -40,7 +41,9 @@ module nanosoc_axi_stream_io_8_rxd_to_file
    
    reg       nxt_end_simulation;
    reg       reg_end_simulation;
-  
+
+assign eof_received = nxt_end_simulation;
+
    initial
      begin
        ready <= 0;
@@ -62,8 +65,10 @@ module nanosoc_axi_stream_io_8_rxd_to_file
            ch = (rxd8_data & 8'hff);
            if  (ch==8'h04) // Stop simulation if 0x04 is received
              nxt_end_simulation <= 1'b1;
-           else
+           else begin
              $fwrite(fd, "%c", ch);
+             if (VERBOSE) $write("%c", ch);
+             end
          end
          $write("** %m : log file closed after stream RX terminated **\n");
          $fclose(fd);

verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v

@@ -147,7 +147,10 @@ localparam BUFSIZE = (64 * 1024);
    $write("** %m : input file length measured as: %d **\n", flen); 
        if (flen > 0) flen=flen-1; // correct for extra char count(???)
        // now output the entire adp buffer to the stream
-       flen = flen + clen+25;
+       if (FAST_LOAD==0)
+           flen = flen + clen+25;
+       else
+           flen = flen + clen+17;
        fp = 0;
        valid <= 0;
        begin