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extio8x4-axis/rtl/extio8x4_axis_initiator.v 0 → 100644
View file @ 5b1ffaf6
//-----------------------------------------------------------------------------
// 8-bit extio transfer over 4-bit data plane - initiator
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Initiator FSM wrapped with synchronizers
//-----------------------------------------------------------------------------
module extio8x4_axis_initiator
(
input wire clk,
input wire resetn,
input wire testmode,
// RX 4-channel AXIS interface
output wire axis_rx0_tready,
input wire axis_rx0_tvalid,
input wire [7:0] axis_rx0_tdata8,
output wire axis_rx1_tready,
input wire axis_rx1_tvalid,
input wire [7:0] axis_rx1_tdata8,
input wire axis_tx0_tready,
output wire axis_tx0_tvalid,
output wire [7:0] axis_tx0_tdata8,
input wire axis_tx1_tready,
output wire axis_tx1_tvalid,
output wire [7:0] axis_tx1_tdata8,
// external io interface
input wire [3:0] iodata4_a,
output wire [3:0] iodata4_o,
output wire [3:0] iodata4_e,
output wire [3:0] iodata4_t,
output wire ioreq1_o,
output wire ioreq2_o,
input wire ioack_a
);
wire ioack_s;
wire [3:0] iodata4_s;
extio8x4_sync u_extio8x4_sync_ioack
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(ioack_a),
.sig_s(ioack_s)
);
extio8x4_sync u_extio8x4_sync_iodata0
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(iodata4_a[0]),
.sig_s(iodata4_s[0])
);
extio8x4_sync u_extio8x4_sync_iodata1
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(iodata4_a[1]),
.sig_s(iodata4_s[1])
);
extio8x4_sync u_extio8x4_sync_iodata2
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(iodata4_a[2]),
.sig_s(iodata4_s[2])
);
extio8x4_sync u_extio8x4_sync_iodata3
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(iodata4_a[3]),
.sig_s(iodata4_s[3])
);
extio8x4_ifsm u_extio8x4_ifsm
(
.clk ( clk ),
.resetn ( resetn ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_a ),
.iodata4_s ( iodata4_s ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_o ( ioreq1_o ),
.ioreq2_o ( ioreq2_o ),
.ioack_s ( ioack_s )
);
endmodule
/*
extio8x4_axis_initiator u_extio8x4_axis_initiator
(
.clk ( clk ),
.resetn ( resetn ),
.testmode ( testmode ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_a ( iodata4_a ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_o ( ioreq1_a ),
.ioreq2_o ( ioreq2_a ),
.ioack_a ( ioack_a )
);
*/
extio8x4-axis/rtl/extio8x4_axis_target.v 0 → 100644
View file @ 5b1ffaf6
//-----------------------------------------------------------------------------
// 8-bit extio transfer over 4-bit data plane - target
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : target FSM wrapped with synchronizers
//-----------------------------------------------------------------------------
module extio8x4_axis_target
(
input wire clk,
input wire resetn,
input wire testmode,
// RX 4-channel AXIS interface
output wire axis_rx0_tready,
input wire axis_rx0_tvalid,
input wire [7:0] axis_rx0_tdata8,
output wire axis_rx1_tready,
input wire axis_rx1_tvalid,
input wire [7:0] axis_rx1_tdata8,
input wire axis_tx0_tready,
output wire axis_tx0_tvalid,
output wire [7:0] axis_tx0_tdata8,
input wire axis_tx1_tready,
output wire axis_tx1_tvalid,
output wire [7:0] axis_tx1_tdata8,
// external io interface
input wire [3:0] iodata4_i,
output wire [3:0] iodata4_o,
output wire [3:0] iodata4_e,
output wire [3:0] iodata4_t,
input wire ioreq1_a,
input wire ioreq2_a,
output wire ioack_o
);
wire ioreq1_s;
wire ioreq2_s;
extio8x4_sync u_extio8x4_sync_ioreq1
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(ioreq1_a),
.sig_s(ioreq1_s)
);
extio8x4_sync u_extio8x4_sync_ioreq2
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(ioreq2_a),
.sig_s(ioreq2_s)
);
extio8x4_tfsm u_extio8x4_tfsm
(
.clk ( clk ),
.resetn ( resetn ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_i ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_s ( ioreq1_s ),
.ioreq2_s ( ioreq2_s ),
.ioack_o ( ioack_o )
);
endmodule
/*
extio8x4_axis_target u_extio8x4_axis_target
(
.clk ( clk ),
.resetn ( resetn ),
.testmode ( testmode ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_i ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_a ( ioreq1_i ),
.ioreq2_a ( ioreq2_i ),
.ioack_o ( ioack_o )
);
*/
extio8x4-axis/rtl/extio8x4_ifsm.v 0 → 100644
View file @ 5b1ffaf6
//-----------------------------------------------------------------------------
// 8-bit extio transfer over 4-bit data plane - initiator
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Initiator state machine and sequencer
//-----------------------------------------------------------------------------
module extio8x4_ifsm
(
input wire clk,
input wire resetn,
// RX 4-channel AXIS interface
output wire axis_rx0_tready,
input wire axis_rx0_tvalid,
input wire [7:0] axis_rx0_tdata8,
output wire axis_rx1_tready,
input wire axis_rx1_tvalid,
input wire [7:0] axis_rx1_tdata8,
input wire axis_tx0_tready,
output wire axis_tx0_tvalid,
output wire [7:0] axis_tx0_tdata8,
input wire axis_tx1_tready,
output wire axis_tx1_tvalid,
output wire [7:0] axis_tx1_tdata8,
// external io interface
input wire [3:0] iodata4_i,
input wire [3:0] iodata4_s,
output wire [3:0] iodata4_o,
output wire [3:0] iodata4_e,
output wire [3:0] iodata4_t,
output wire ioreq1_o,
output wire ioreq2_o,
input wire ioack_s
);
// Fair priority sequencer
// return next 12 transactions - to support 1,2,3 and 4 requests
function [23:0] FNpriority_seq12x2;
input [3:0] req4;
case (req4[3:0])
4'b0001: FNpriority_seq12x2 = 24'b00_00_00_00_00_00_00_00_00_00_00_00; // chan 0
4'b0010: FNpriority_seq12x2 = 24'b01_01_01_01_01_01_01_01_01_01_01_01; // chan 1
4'b0011: FNpriority_seq12x2 = 24'b01_00_01_00_01_00_01_00_01_00_01_00; // chan 0/1
4'b0100: FNpriority_seq12x2 = 24'b10_10_10_10_10_10_10_10_10_10_10_10; // chan 2
4'b0101: FNpriority_seq12x2 = 24'b10_00_10_00_10_00_10_00_10_00_10_00; // chan 0/2
4'b0110: FNpriority_seq12x2 = 24'b10_01_10_01_10_01_10_01_10_01_10_01; // chan 1/2
4'b0111: FNpriority_seq12x2 = 24'b10_01_00_10_01_00_10_01_00_10_01_00; // chan 0/1/2
4'b1000: FNpriority_seq12x2 = 24'b11_11_11_11_11_11_11_11_11_11_11_11; // chan 3
4'b1001: FNpriority_seq12x2 = 24'b11_00_11_00_11_00_11_00_11_00_11_00; // chan 0/3
4'b1010: FNpriority_seq12x2 = 24'b11_01_11_01_11_01_11_01_11_01_11_01; // chan 1/3
4'b1011: FNpriority_seq12x2 = 24'b11_01_00_11_01_00_11_01_00_11_01_00; // chan 0/1/3
4'b1100: FNpriority_seq12x2 = 24'b11_10_11_10_11_10_11_10_11_10_11_10; // chan 2/3
4'b1101: FNpriority_seq12x2 = 24'b11_10_00_11_10_00_11_10_00_11_10_00; // chan 0/2/3
4'b1110: FNpriority_seq12x2 = 24'b11_10_01_11_10_01_11_10_01_11_10_01; // chan 1/2/3
4'b1111: FNpriority_seq12x2 = 24'b11_10_01_00_11_10_01_00_11_10_01_00; // chan 0/1/2/3
default: FNpriority_seq12x2 = 24'b0; // (no requests)
endcase
endfunction
function [1:0] FNmap_patt2code2;
input [23:0] priority_seq12x2;
input [3:0] seq12_no;
case (seq12_no[3:0])
4'b0000: FNmap_patt2code2 = priority_seq12x2[ 1: 0];
4'b0001: FNmap_patt2code2 = priority_seq12x2[ 3: 2];
4'b0010: FNmap_patt2code2 = priority_seq12x2[ 5: 4];
4'b0011: FNmap_patt2code2 = priority_seq12x2[ 7: 6];
4'b0100: FNmap_patt2code2 = priority_seq12x2[ 9: 8];
4'b0101: FNmap_patt2code2 = priority_seq12x2[11:10];
4'b0110: FNmap_patt2code2 = priority_seq12x2[13:12];
4'b0111: FNmap_patt2code2 = priority_seq12x2[15:14];
4'b1000: FNmap_patt2code2 = priority_seq12x2[17:16];
4'b1001: FNmap_patt2code2 = priority_seq12x2[19:18];
4'b1010: FNmap_patt2code2 = priority_seq12x2[21:20];
4'b1011: FNmap_patt2code2 = priority_seq12x2[23:22];
default: FNmap_patt2code2 = 2'b00; // (illegal seq no)
endcase
endfunction
reg ack;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
ack <= 1'b0;
else
ack <= ioack_s;
end
wire ack_change = ack ^ ioack_s;
// state[0] = ioreq1
// state[1] = ioreq2
// state[2] = CTL4_EN
// state[3] = WD4H_EN
// state[4] = WD4L_EN
// state[5] = WDONE
// state[6] = RD4H_EN
// state[7] = RD4L_EN
// state[8] = RXDONE
// state[9] = TX
localparam STAT = 10'b0_000_0000_00;
localparam RXC1 = 10'b0_000_0000_01;
localparam RXC2 = 10'b0_000_0001_11;
localparam RXDH = 10'b0_001_0000_01;
localparam RXDL = 10'b0_010_0000_11;
localparam RXDZ = 10'b0_100_0000_01;
localparam TXDH = 10'b1_000_0010_01;
localparam TXDL = 10'b1_000_0100_11;
localparam TXDZ = 10'b1_000_1000_01;
reg [9:0] fsm_state;
reg [9:0] nxt_fsm_state;
reg [3:0] cmd4;
wire start_xfer;
// ifsm next-state seqeuncer
always @(*)
case (fsm_state)
STAT: nxt_fsm_state = (!ioack_s & (start_xfer)) ? RXC1 : STAT;
RXC1: nxt_fsm_state = ( ioack_s) ? RXC2 : RXC1;
RXC2: nxt_fsm_state = (!ioack_s) ? ((cmd4[0]) ? RXDH : TXDH) : RXC2;
RXDH: nxt_fsm_state = ( ioack_s) ? RXDL : RXDH;
RXDL: nxt_fsm_state = (!ioack_s) ? RXDZ : RXDL;
RXDZ: nxt_fsm_state = ( ioack_s) ? STAT : RXDZ;
TXDH: nxt_fsm_state = ( ioack_s) ? TXDL : TXDH;
TXDL: nxt_fsm_state = (!ioack_s) ? TXDZ : TXDL;
TXDZ: nxt_fsm_state = ( ioack_s) ? STAT : TXDZ;
default: nxt_fsm_state = STAT;
endcase
// state update
always @(posedge clk or negedge resetn)
begin
if (!resetn) begin
fsm_state <= 10'h000;
end else begin
fsm_state <= nxt_fsm_state;
end
end
wire status_valid = !fsm_state[0];
// stream buffers with valid qualifiers
reg [8:0] rx0_reg9;
reg [8:0] rx1_reg9;
reg [8:0] tx0_reg9;
reg [8:0] tx1_reg9;
// axis request per channel to FSM, hold until ack
wire rx0_axis_req;
wire rx1_axis_req;
wire tx0_axis_req;
wire tx1_axis_req;
// axis request acknowledge per channel, from FSM, 1-cycle pulse
wire rx0_axis_ack;
wire rx1_axis_ack;
wire tx0_axis_ack;
wire tx1_axis_ack;
reg req_rx0;
reg req_rx1;
reg req_tx0;
reg req_tx1;
// data ports
wire [7:0] tx_axis_rdata8;
wire [7:0] rx0_axis_wdata8;
wire [7:0] rx1_axis_wdata8;
// axis RX1 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rx0_reg9 <= 9'b0_00000000;
else begin
if (!rx0_reg9[8] & axis_rx0_tvalid) rx0_reg9 <= {1'b1,axis_rx0_tdata8[7:0]};
else if (rx0_reg9[8] & rx0_axis_ack) rx0_reg9[8] <= 1'b0;
end
end
assign axis_rx0_tready = !rx0_reg9[8];
assign rx0_axis_wdata8 = rx0_reg9[7:0];
assign rx0_axis_req = rx0_reg9[8];
// axis RX2 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rx1_reg9 <= 9'b0_00000000;
else begin
if (!rx1_reg9[8] & axis_rx1_tvalid) rx1_reg9 <= {1'b1,axis_rx1_tdata8[7:0]};
else if (rx1_reg9[8] & rx1_axis_ack) rx1_reg9[8] <= 1'b0;
end
end
assign axis_rx1_tready = !rx1_reg9[8];
assign rx1_axis_wdata8 = rx1_reg9[7:0];
assign rx1_axis_req = rx1_reg9[8];
// axis TX1 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
tx0_reg9 <= 9'b0_00000000;
else begin
if (!tx0_reg9[8] & tx0_axis_ack) tx0_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
else if (tx0_reg9[8] & axis_tx0_tready) tx0_reg9[8] <= 1'b0;
end
end
assign axis_tx0_tvalid = tx0_reg9[8];
assign axis_tx0_tdata8[7:0] = tx0_reg9[7:0];
assign tx0_axis_req = !tx0_reg9[8];
// axis tx2 port interextio8x4_ifsmface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
tx1_reg9 <= 9'b0_00000000;
else begin
if (!tx1_reg9[8] & tx1_axis_ack) tx1_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
else if (tx1_reg9[8] & axis_tx1_tready) tx1_reg9[8] <= 1'b0;
end
end
assign axis_tx1_tvalid = tx1_reg9[8];
assign axis_tx1_tdata8[7:0] = tx1_reg9[7:0];
assign tx1_axis_req = !tx1_reg9[8];
// virtual channel requests, only valid during status phase
wire vtx0_req = status_valid & !iodata4_s[0] & req_tx0;
wire vrx0_req = status_valid & !iodata4_s[1] & req_rx0;
wire vtx1_req = status_valid & !iodata4_s[2] & req_tx1;
wire vrx1_req = status_valid & !iodata4_s[3] & req_rx1;
wire [3:0] active_req4 = {vtx1_req, vrx1_req, vtx0_req, vrx0_req};
// any active request
wire cmd4_req = (vtx0_req | vrx0_req | vtx1_req | vrx1_req);
assign start_xfer = (cmd4_req & !ioack_s);
// 12 cycle sequencer counter
reg [3:0] seq_cnt12;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
seq_cnt12 <= 4'b0000;
else
if (start_xfer) seq_cnt12 <= (seq_cnt12 >= 11) ? 4'b0000 : (seq_cnt12+4'b0001);
end
wire [3:0] cmd4_nxt;
// command resister
always @(posedge clk or negedge resetn)
begin
if (!resetn)
cmd4 <= 4'b0000; // invalid xfer pattern
else if (cmd4_req)
cmd4 <= cmd4_nxt;
end
// simplest fixed priority scheme: RX0, RX1, TX0, TX1 (decreasing)
/*
assign cmd4_nxt[0] = (vrx0_req | vrx1_req); // Read/not-write always has priority
assign cmd4_nxt[1] = !(vrx0_req | vtx0_req);
*/
assign cmd4_nxt[1:0] = FNmap_patt2code2(FNpriority_seq12x2(active_req4), seq_cnt12);
/* */
assign cmd4_nxt[3:2] = 2'b00; // fixed 8-bit transfer
// write data resister - for the committed channel
reg [7:0] wdata8;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
wdata8 <= 8'b00000000; // avoid X propagation
else if (start_xfer & !cmd4_nxt[0]) // capture selected wdata
wdata8 <= (cmd4_nxt[1]) ? rx1_axis_wdata8[7:0] : rx0_axis_wdata8[7:0];
end
// request handshake
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_rx0 <= 1'b0; // avoid X propagation
else if (rx0_axis_req & !req_rx0) // capture rx_req front edge
req_rx0 <= 1'b1;
else if (rx0_axis_ack & req_rx0)
req_rx0 <= 1'b0;
end
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_rx1 <= 1'b0; // avoid X propagation
else if (rx1_axis_req & !req_rx1) // capture rx_req front edge
req_rx1 <= 1'b1;
else if (rx1_axis_ack & req_rx1)
req_rx1 <= 1'b0;
end
// request handshake
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_tx0 <= 1'b0; // avoid X propagation
else if (tx0_axis_req & !req_tx0) // capture tx_req front edge
req_tx0 <= 1'b1;
else if (tx0_axis_ack & req_tx0)
req_tx0 <= 1'b0;
end
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_tx1 <= 1'b0; // avoid X propagation
else if (tx1_axis_req & !req_tx1) // capture tx_req front edge
req_tx1 <= 1'b1;
else if (tx1_axis_ack & req_tx1)
req_tx1 <= 1'b0;
end
// fsm decodes:
// request signalling
assign ioreq1_o = fsm_state[0];
assign ioreq2_o = fsm_state[1];
// dataout mux
wire cmd_state = fsm_state[2];
wire wdh_state = fsm_state[3];
wire wdl_state = fsm_state[4];
wire wdone = fsm_state[5];
// datain sel
wire rdh_state = fsm_state[6];
wire rdl_state = fsm_state[7];
wire rdone = fsm_state[8];
// IO Write Data
assign iodata4_o = ({4{cmd_state}} & cmd4)
| ({4{wdh_state}} & wdata8[7:4])
| ({4{wdl_state}} & wdata8[3:0])
| ({4{wdone}} & wdata8[3:0])
;
assign iodata4_e = {4{|(fsm_state[4:2])}};
assign iodata4_t = ~iodata4_e;
// and ack
assign rx0_axis_ack = !cmd4[1] & !cmd4[0] & wdone & ack_change;
assign rx1_axis_ack = cmd4[1] & !cmd4[0] & wdone & ack_change;
// IO Read data
// first register high nibble read data
reg [3:0] rd4_hi;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rd4_hi <= 4'b0000; // initialize
else if (rdh_state & ack_change)
rd4_hi <= iodata4_i[3:0];
end
reg [3:0] rd4_lo;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rd4_lo <= 4'b0000; // initialize
else if (rdl_state & ack_change)
rd4_lo <= iodata4_i[3:0];
end
assign tx_axis_rdata8 = {rd4_hi[3:0],rd4_lo[3:0]};
// then ack with 8-bit data to selected axis buffer
assign tx0_axis_ack = !cmd4[1] & cmd4[0] & rdone & ack_change;
assign tx1_axis_ack = cmd4[1] & cmd4[0] & rdone & ack_change;
endmodule
/*
extio8x4_ifsm u_extio8x4_ifsm
(
.clk ( clk ),
.resetn ( resetn ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_i ),
.iodata4_s ( iodata4_s ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_o ( ioreq1_o ),
.ioreq2_o ( ioreq2_o ),
.ioack_s ( ioack_s )
);
*/
extio8x4-axis/rtl/extio8x4_sync.v 0 → 100644
View file @ 5b1ffaf6
//-----------------------------------------------------------------------------
// 8-bit extio transfer over 4-bit data plane - initiator
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module extio8x4_sync
(
input wire clk,
input wire resetn,
input wire testmode,
input wire sig_a,
output wire sig_s
);
reg [2:1] sig_r;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
sig_r <= 2'b00; // default
else
sig_r <= {sig_r[1], sig_a}; // shift left
end
assign sig_s = (testmode) ? sig_a : sig_r[2];
endmodule
/*
extio8x4_sync, u_extio8x4_sync_1
(
.clk(clk),
.resetn(resetn),
.testmode(testmode),
.sig_a(sig_i),
.sig_s(sig_s)
);
*/
extio8x4-axis/rtl/extio8x4_tfsm.v 0 → 100644
View file @ 5b1ffaf6
//-----------------------------------------------------------------------------
// 8-bit extio transfer over 4-bit data plane - target
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Initiator state machine and sequencer
//-----------------------------------------------------------------------------
module extio8x4_tfsm
(
input wire clk,
input wire resetn,
// RX 4-channel AXIS interface
output wire axis_rx0_tready,
input wire axis_rx0_tvalid,
input wire [7:0] axis_rx0_tdata8,
output wire axis_rx1_tready,
input wire axis_rx1_tvalid,
input wire [7:0] axis_rx1_tdata8,
input wire axis_tx0_tready,
output wire axis_tx0_tvalid,
output wire [7:0] axis_tx0_tdata8,
input wire axis_tx1_tready,
output wire axis_tx1_tvalid,
output wire [7:0] axis_tx1_tdata8,
// external io interface
input wire [3:0] iodata4_i,
output wire [3:0] iodata4_o,
output wire [3:0] iodata4_e,
output wire [3:0] iodata4_t,
input wire ioreq1_s,
input wire ioreq2_s,
output wire ioack_o
);
// axis request per channel to FSM, hold until ack
wire rx0_axis_req;
wire rx1_axis_req;
wire tx0_axis_req;
wire tx1_axis_req;
// axis request acknowledge per channel, from FSM, 1-cycle pulse
wire rx0_axis_ack;
wire rx1_axis_ack;
wire tx0_axis_ack;
wire tx1_axis_ack;
reg req_rx0;
reg req_rx1;
reg req_tx0;
reg req_tx1;
// data ports
wire [7:0] tx_axis_rdata8;
wire [7:0] rx0_axis_wdata8;
wire [7:0] rx1_axis_wdata8;
wire ack_nxt = ioreq1_s ^ ioreq2_s;
reg ack;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
ack <= 1'b0;
else
ack <= ack_nxt;
end
wire ack_change = ack ^ ack_nxt;
// state[0] = ACK
// state[1] = CTL4_EN
// state[2] = RD4H_EN
// state[3] = RD4L_EN
// state[4] = STAT_EN
// state[5] = WD4H_EN
// state[6] = WD4L_EN
localparam STAT = 8'b0_001_000_0;
localparam RXC1 = 8'b0_000_001_1;
localparam RXDH = 8'b0_000_010_0;
localparam RXDL = 8'b0_000_100_1;
localparam RXDZ = 8'b0_000_000_0;
localparam STAZ = 8'b0_001_000_1;
localparam TXCZ = 8'b1_000_000_0;
localparam TXDH = 8'b1_010_000_1;
localparam TXDL = 8'b1_100_000_0;
reg [7:0] fsm_state;
reg [7:0] nxt_fsm_state;
// ifsm next-state seqeuncer
always @(*)
case (fsm_state)
STAT: nxt_fsm_state = ( ioreq1_s) ? RXC1 : STAT;
RXC1: nxt_fsm_state = (!ioreq2_s) ? RXC1 : (iodata4_i[0]) ? TXCZ : RXDH;
RXDH: nxt_fsm_state = ( ioreq2_s) ? RXDH : RXDL;
RXDL: nxt_fsm_state = (!ioreq2_s) ? RXDL : RXDZ;
RXDZ: nxt_fsm_state = ( ioreq2_s) ? RXDZ : STAZ;
STAZ: nxt_fsm_state = ( ioreq1_s) ? STAZ : STAT;
TXCZ: nxt_fsm_state = ( ioreq2_s) ? TXCZ : TXDH;
TXDH: nxt_fsm_state = (!ioreq2_s) ? TXDH : TXDL;
TXDL: nxt_fsm_state = ( ioreq2_s) ? TXDL : STAZ;
default: nxt_fsm_state = STAT;
endcase
// state update
always @(posedge clk or negedge resetn)
begin
if (!resetn) begin
fsm_state <= STAT;
end else
fsm_state <= nxt_fsm_state;
end
assign ioack_o = fsm_state[0];
// 3 input sample enable
wire cmd_state = fsm_state[1];
wire rdh_state = fsm_state[2];
wire rdl_state = fsm_state[3];
// 3 output enable
wire fif_state = fsm_state[4];
wire wdh_state = fsm_state[5];
wire wdl_state = fsm_state[6];
// command resister
reg [3:0] cmd4;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
cmd4 <= 4'b1111; // invalid xfer pattern
else if (cmd_state & ack_change)
cmd4 <= iodata4_i[3:0];
end
wire [3:0] fifo_stat = ~{req_tx1, req_rx1, req_tx0, req_rx0 };
// IO Write Data
assign iodata4_o = ({4{fif_state}} & fifo_stat)
| ({4{wdh_state}} & ((cmd4[1]) ? rx1_axis_wdata8[7:4] : rx0_axis_wdata8[7:4]))
| ({4{wdl_state}} & ((cmd4[1]) ? rx1_axis_wdata8[3:0] : rx0_axis_wdata8[3:0]))
;
assign iodata4_e = {4{|(fsm_state[6:4])}};
assign iodata4_t = {4{!iodata4_e}};
// and ack
assign rx0_axis_ack = !cmd4[1] & cmd4[0] & wdl_state & ack_change;
assign rx1_axis_ack = cmd4[1] & cmd4[0] & wdl_state & ack_change;
// IO Read data
// first register high nibble read data
reg [3:0] rd4_hi;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rd4_hi <= 4'b0000; // initialize
else if (rdh_state & ack_change)
rd4_hi <= iodata4_i[3:0];
end
assign tx_axis_rdata8 = {rd4_hi[3:0],iodata4_i[3:0]};
// then ack with 8-bit data to selected axis buffer
assign tx0_axis_ack = !cmd4[1] & !cmd4[0] & rdl_state & ack_change;
assign tx1_axis_ack = cmd4[1] & !cmd4[0] & rdl_state & ack_change;
// stream buffers with valid qualifiers
reg [8:0] rx0_reg9;
reg [8:0] rx1_reg9;
reg [8:0] tx0_reg9;
reg [8:0] tx1_reg9;
// axis RX1 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rx0_reg9 <= 9'b0_00000000;
else begin
if (!rx0_reg9[8] & axis_rx0_tvalid) rx0_reg9 <= {1'b1,axis_rx0_tdata8[7:0]};
else if (rx0_reg9[8] & rx0_axis_ack) rx0_reg9[8] <= 1'b0;
end
end
assign axis_rx0_tready = !rx0_reg9[8];
assign rx0_axis_wdata8 = rx0_reg9[7:0];
assign rx0_axis_req = rx0_reg9[8] & !fsm_state[2] & !fsm_state[3];
// axis RX2 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
rx1_reg9 <= 9'b0_00000000;
else begin
if (!rx1_reg9[8] & axis_rx1_tvalid) rx1_reg9 <= {1'b1,axis_rx1_tdata8[7:0]};
else if (rx1_reg9[8] & rx1_axis_ack) rx1_reg9[8] <= 1'b0;
end
end
assign axis_rx1_tready = !rx1_reg9[8];
assign rx1_axis_wdata8 = rx1_reg9[7:0];
assign rx1_axis_req = rx1_reg9[8] & !fsm_state[2] & !fsm_state[3];
// axis TX1 port interface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
tx0_reg9 <= 9'b0_00000000;
else begin
if (!tx0_reg9[8] & tx0_axis_ack) tx0_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
else if (tx0_reg9[8] & axis_tx0_tready) tx0_reg9[8] <= 1'b0;
end
end
assign axis_tx0_tvalid = tx0_reg9[8];
assign axis_tx0_tdata8[7:0] = tx0_reg9[7:0];
assign tx0_axis_req = !tx0_reg9[8];
// axis tx2 port interextio8x4_ifsmface
always @(posedge clk or negedge resetn)
begin
if (!resetn)
tx1_reg9 <= 9'b0_00000000;
else begin
if (!tx1_reg9[8] & tx1_axis_ack) tx1_reg9 <= {1'b1,tx_axis_rdata8[7:0]};
else if (tx1_reg9[8] & axis_tx1_tready) tx1_reg9[8] <= 1'b0;
end
end
assign axis_tx1_tvalid = tx1_reg9[8];
assign axis_tx1_tdata8[7:0] = tx1_reg9[7:0];
assign tx1_axis_req = !tx1_reg9[8];
// request handshake
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_rx0 <= 1'b0; // avoid X propagation
else if (rx0_axis_req & !req_rx0) // capture rx_req front edge
req_rx0 <= 1'b1;
else if (rx0_axis_ack & req_rx0)
req_rx0 <= 1'b0;
end
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_rx1 <= 1'b0; // avoid X propagation
else if (rx1_axis_req & !req_rx1) // capture rx_req front edge
req_rx1 <= 1'b1;
else if (rx1_axis_ack & req_rx1)
req_rx1 <= 1'b0;
end
// request handshake
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_tx0 <= 1'b0; // avoid X propagation
else if (tx0_axis_req & !req_tx0) // capture tx_req front edge
req_tx0 <= 1'b1;
else if (tx0_axis_ack & req_tx0)
req_tx0 <= 1'b0;
end
always @(posedge clk or negedge resetn)
begin
if (!resetn)
req_tx1 <= 1'b0; // avoid X propagation
else if (tx1_axis_req & !req_tx1) // capture tx_req front edge
req_tx1 <= 1'b1;
else if (tx1_axis_ack & req_tx1)
req_tx1 <= 1'b0;
end
endmodule
/*
extio8x4_ifsm u_extio8x4_tfsm
(
.clk ( clk ),
.resetn ( resetn ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_i ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_s ( ioreq1_s ),
.ioreq2_s ( ioreq2_s ),
.ioack_o ( ioack_o )
);
*/
flist/nanosoc.flist
View file @ 5b1ffaf6
......@@ -20,6 +20,9 @@
// NanoSoC Chip Pads Level
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
......
flist/nanosoc_tb.flist
View file @ 5b1ffaf6
......@@ -19,9 +19,11 @@
// - Top-level testbench
$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_target.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_tfsm.v
// Include NanoSoC Testbench Components
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist
// Include Corstone VIP Components
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
\ No newline at end of file
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
flist/nanosoc_vip.flist
View file @ 5b1ffaf6
......@@ -20,10 +20,11 @@
$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/soclabs_axis8_capture.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
\ No newline at end of file
$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
View file @ 5b1ffaf6
......@@ -74,31 +74,14 @@ module nanosoc_chip #(
wire CPU_0_SWDO; // SWD data output
wire CPU_0_SWDOEN; // SWD data enable
// FT1248 Interace - FT1248
wire FT_CLK_O; // SCLK
wire FT_SSN_O; // SS_N
wire FT_MISO_I; // MISO
wire [FT1248_WIDTH-1:0] FT_MIOSIO_O; // MIOSIO tristate when enabled
wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate enable (active hi)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate enable (active lo)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
// GPIO interface
wire [7:0] GPO8;
wire [7:0] GPI8;
// GPIO
wire [15:0] P0_IN; // GPIO 0 inputs
wire [15:0] P0_OUT; // GPIO 0 outputs
wire [15:0] P0_OUTEN; // GPIO 0 output enables
wire [15:0] P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
wire [15:0] P1_IN_MUX; // level-shifted input from pad
wire [15:0] P1_IN; // level-shifted input from pad
wire [15:0] P1_OUT; // GPIO 1 outputs
wire [15:0] P1_OUTEN; // GPIO 1 output enables
wire [15:0] P1_OUT_MUX; // GPIO 1 aOutput Port Drive
wire [15:0] P1_OUT_EN_MUX; // Active High output drive enable (pad tech dependent)
wire [15:0] P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
//--------------------------
// FPGA-Specific Wiring - Should be own Module
......@@ -141,50 +124,20 @@ module nanosoc_chip #(
assign swdio_z = !CPU_0_SWDOEN;
//--------------------------
// FT1248 Wiring
// PIO pad control
//--------------------------
assign P0_IN = p0_i;
assign p0_o = P0_OUT;
assign p0_e = P0_OUTEN;
assign p0_z = ~P0_OUTEN;
assign FT_MISO_I = p1_i[0]; // FT_MISO INPUT pad configuration
assign P1_IN_MUX[0] = p1_i[0];
assign p1_o[0] = 1'b0;
assign p1_e[0] = 1'b0;
assign p1_z[0] = 1'b1;
assign P1_IN_MUX[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
assign p1_o[1] = FT_CLK_O;
assign p1_e[1] = 1'b1;
assign p1_z[1] = 1'b0;
assign FT_MIOSIO_I = p1_i[2]; // FT_MIOSIO INOUT pad configuration
assign P1_IN_MUX[2] = p1_i[2];
assign p1_o[2] = FT_MIOSIO_O;
assign p1_e[2] = FT_MIOSIO_E;
assign p1_z[2] = FT_MIOSIO_Z;
assign P1_IN_MUX[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
assign p1_o[3] = FT_SSN_O;
assign p1_e[3] = 1'b1;
assign p1_z[3] = 1'b0;
assign P1_IN_MUX[4] = (alt_mode) ? uart_rxd_i : p1_i[4]; // RXD2
assign uart_txd_o = P1_OUT_MUX[5]; // TXD2
assign P1_IN = p1_i;
assign p1_o[15:0] = P1_OUT[15:0];
assign p1_e[15:0] = P1_OUTEN[15:0];
assign p1_z[15:0] = ~P1_OUTEN[15:0];
assign P1_IN_MUX[15:5] = p1_i[15:5]; // IO MUX controlled bidirectionals
assign p1_o[15:4] = P1_OUT_MUX[15:4];
assign p1_e[15:4] = P1_OUT_EN_MUX[15:4];
assign p1_z[15:4] = ~P1_OUT_EN_MUX[15:4];
//--------------------------
// GPIO Interface Assignment
//--------------------------
assign GPI8 = GPO8;
//--------------------------
// System Instantiation
//--------------------------
......@@ -207,30 +160,13 @@ module nanosoc_chip #(
.CPU_0_SWDO(CPU_0_SWDO),
.CPU_0_SWDOEN(CPU_0_SWDOEN),
// FT1248 Interace - FT1248
.FT_CLK_O(FT_CLK_O),
.FT_SSN_O(FT_SSN_O),
.FT_MISO_I(FT_MISO_I),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
// GPIO interface
.GPO8(GPO8),
.GPI8(GPI8),
// GPIO
.P0_IN(P0_IN),
.P0_OUT(P0_OUT),
.P0_OUTEN(P0_OUTEN),
.P0_ALTFUNC(P0_ALTFUNC),
.P1_IN(P1_IN_MUX),
.P1_IN(P1_IN), //_MUX),
.P1_OUT(P1_OUT),
.P1_OUTEN(P1_OUTEN),
.P1_ALTFUNC(P1_ALTFUNC),
.P1_OUT_MUX(P1_OUT_MUX),
.P1_OUT_EN_MUX(P1_OUT_EN_MUX)
.P1_OUTEN(P1_OUTEN)
);
endmodule
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
View file @ 5b1ffaf6
......@@ -82,12 +82,29 @@ module nanosoc_region_sysio #(
output wire PMUENABLE, // System Controller cfg - Enable PMU
// IO signalling
input wire uart0_rxd, // Uart 0 receive data
output wire uart0_txd, // Uart 0 transmit data
output wire uart0_txen, // Uart 0 transmit data enable
input wire uart1_rxd, // Uart 1 receive data
output wire uart1_txd, // Uart 1 transmit data
output wire uart1_txen, // Uart 1 transmit data enable
// input wire uart0_rxd, // Uart 0 receive data
// output wire uart0_txd, // Uart 0 transmit data
// output wire uart0_txen, // Uart 0 transmit data enable
// USRT0 TXD axi byte stream
output wire usrt0_txd_tvalid,
output wire [ 7:0] usrt0_txd_tdata,
input wire usrt0_txd_tready,
// USRT0 RXD axi byte stream
input wire usrt0_rxd_tvalid,
input wire [ 7:0] usrt0_rxd_tdata,
output wire usrt0_rxd_tready,
// input wire uart1_rxd, // Uart 1 receive data
// output wire uart1_txd, // Uart 1 transmit data
// output wire uart1_txen, // Uart 1 transmit data enable
// USRT1 TXD axi byte stream
output wire usrt1_txd_tvalid,
output wire [ 7:0] usrt1_txd_tdata,
input wire usrt1_txd_tready,
// USRT1 RXD axi byte stream
input wire usrt1_rxd_tvalid,
input wire [ 7:0] usrt1_rxd_tdata,
output wire usrt1_rxd_tready,
//UART2
input wire uart2_rxd, // Uart 2 receive data
output wire uart2_txd, // Uart 2 transmit data
output wire uart2_txen, // Uart 2 transmit data enable
......@@ -375,8 +392,8 @@ module nanosoc_region_sysio #(
.INCLUDE_APB_TIMER0 (1), // Include simple timer #0
.INCLUDE_APB_TIMER1 (1), // Include simple timer #1
.INCLUDE_APB_DUALTIMER0 (1), // Include dual timer module
.INCLUDE_APB_UART0 (0), // Exclude simple UART #0
.INCLUDE_APB_UART1 (0), // Exclude simple UART #1
.INCLUDE_APB_USRT0 (1), // Replace simple UART #0 with USRT0
.INCLUDE_APB_USRT1 (1), // Replace simple UART #1 with USRT1
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
......@@ -433,13 +450,25 @@ module nanosoc_region_sysio #(
// Peripherals
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
// .uart0_rxd (uart0_rxd),
// .uart0_txd (uart0_txd),
// .uart0_txen (uart0_txen),
.usrt0_txd_tvalid (usrt0_txd_tvalid),
.usrt0_txd_tdata (usrt0_txd_tdata ),
.usrt0_txd_tready (usrt0_txd_tready),
.usrt0_rxd_tvalid (usrt0_rxd_tvalid),
.usrt0_rxd_tdata (usrt0_rxd_tdata ),
.usrt0_rxd_tready (usrt0_rxd_tready),
// .uart1_rxd (uart1_rxd),
// .uart1_txd (uart1_txd),
// .uart1_txen (uart1_txen),
.usrt1_txd_tvalid (usrt1_txd_tvalid),
.usrt1_txd_tdata (usrt1_txd_tdata ),
.usrt1_txd_tready (usrt1_txd_tready),
.usrt1_rxd_tvalid (usrt1_rxd_tvalid),
.usrt1_rxd_tdata (usrt1_rxd_tdata ),
.usrt1_rxd_tready (usrt1_rxd_tready),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
......
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
View file @ 5b1ffaf6
......@@ -59,8 +59,8 @@ module nanosoc_sysio_apb_ss #(
parameter INCLUDE_APB_TIMER0 = 1, // Include simple timer #0
parameter INCLUDE_APB_TIMER1 = 1, // Include simple timer #1
parameter INCLUDE_APB_DUALTIMER0 = 1, // Include dual timer module
parameter INCLUDE_APB_UART0 = 1, // Include simple UART #0
parameter INCLUDE_APB_UART1 = 1, // Include simple UART #1
parameter INCLUDE_APB_USRT0 = 1, // Include simple UART #0
parameter INCLUDE_APB_USRT1 = 1, // Include simple UART #1
parameter INCLUDE_APB_UART2 = 1, // Include simple UART #2.
// Note : UART #2 is required for text messages
// display and to enable debug tester in
......@@ -139,15 +139,32 @@ module nanosoc_sysio_apb_ss #(
output wire APBACTIVE,
// Peripherals
// UART
input wire uart0_rxd,
output wire uart0_txd,
output wire uart0_txen,
input wire uart1_rxd,
output wire uart1_txd,
output wire uart1_txen,
// USRT0
// input wire uart0_rxd,
// output wire uart0_txd,
// output wire uart0_txen,
// USRT0 TXD axi byte stream
output wire usrt0_txd_tvalid,
output wire [ 7:0] usrt0_txd_tdata,
input wire usrt0_txd_tready,
// USRT0 RXD axi byte stream
input wire usrt0_rxd_tvalid,
input wire [ 7:0] usrt0_rxd_tdata,
output wire usrt0_rxd_tready,
// input wire uart1_rxd,
// output wire uart1_txd,
// output wire uart1_txen,
// USRT1 TXD axi byte stream
output wire usrt1_txd_tvalid,
output wire [ 7:0] usrt1_txd_tdata,
input wire usrt1_txd_tready,
// USRT1 RXD axi byte stream
input wire usrt1_rxd_tvalid,
input wire [ 7:0] usrt1_rxd_tdata,
output wire usrt1_rxd_tready,
// UART2
input wire uart2_rxd,
output wire uart2_txd,
output wire uart2_txen,
......@@ -354,8 +371,8 @@ module nanosoc_sysio_apb_ss #(
.PORT1_ENABLE (INCLUDE_APB_TIMER1), // timer 1
.PORT2_ENABLE (INCLUDE_APB_DUALTIMER0), // dual timer 0
.PORT3_ENABLE (1), // not used
.PORT4_ENABLE (INCLUDE_APB_UART0), // uart 0
.PORT5_ENABLE (INCLUDE_APB_UART1), // uart 1
.PORT4_ENABLE (INCLUDE_APB_USRT0), // uart 0
.PORT5_ENABLE (INCLUDE_APB_USRT1), // uart 1
.PORT6_ENABLE (INCLUDE_APB_UART2), // uart 2
.PORT7_ENABLE (1), // not used
.PORT8_ENABLE (INCLUDE_APB_WATCHDOG), // watchdog
......@@ -601,8 +618,8 @@ module nanosoc_sysio_apb_ss #(
// -----------------------------------------------------------------
// UARTs
generate if (INCLUDE_APB_UART0 == 1) begin : gen_apb_uart_0
cmsdk_apb_uart u_apb_uart_0 (
generate if (INCLUDE_APB_USRT0 == 1) begin : gen_apb_uart_0
socdebug_usrt_control u_apb_usrt_0 (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
......@@ -619,12 +636,22 @@ module nanosoc_sysio_apb_ss #(
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
.RXD (uart0_rxd), // Receive data
// .RXD (uart0_rxd), // Receive data
//
// .TXD (uart0_txd), // Transmit data
// .TXEN (uart0_txen), // Transmit Enabled
//
// .BAUDTICK (), // Baud rate x16 tick output (for testing)
.TXD (uart0_txd), // Transmit data
.TXEN (uart0_txen), // Transmit Enabled
// USRT0 Interface - From USRT TXD
.TX_VALID_o (usrt0_txd_tvalid),
.TX_DATA8_o (usrt0_txd_tdata),
.TX_READY_i (usrt0_txd_tready),
.BAUDTICK (), // Baud rate x16 tick output (for testing)
// USRT1 Interface - To USRT RXD
.RX_VALID_i (usrt0_rxd_tvalid),
.RX_DATA8_i (usrt0_rxd_tdata),
.RX_READY_o (usrt0_rxd_tready),
.TXINT (uart0_txint), // Transmit Interrupt
.RXINT (uart0_rxint), // Receive Interrupt
......@@ -637,8 +664,11 @@ module nanosoc_sysio_apb_ss #(
assign uart0_prdata = {32{1'b0}};
assign uart0_pready = 1'b1;
assign uart0_pslverr = 1'b0;
assign uart0_txd = 1'b1;
assign uart0_txen = 1'b0;
// assign uart0_txd = 1'b1;
// assign uart0_txen = 1'b0;
assign usrt0_txd_tvalid = 1'b0;
assign usrt0_txd_tdata = {8{1'b0}};
assign usrt0_rxd_tready = 1'b0;
assign uart0_txint = 1'b0;
assign uart0_rxint = 1'b0;
assign uart0_txovrint = 1'b0;
......@@ -646,8 +676,8 @@ module nanosoc_sysio_apb_ss #(
assign uart0_combined_int = 1'b0;
end endgenerate
generate if (INCLUDE_APB_UART1 == 1) begin : gen_apb_uart_1
cmsdk_apb_uart u_apb_uart_1 (
generate if (INCLUDE_APB_USRT1 == 1) begin : gen_apb_uart_1
socdebug_usrt_control u_apb_usrt_1 (
.PCLK (PCLK), // Peripheral clock
.PCLKG (PCLKG), // Gated PCLK for bus
.PRESETn (PRESETn), // Reset
......@@ -664,12 +694,20 @@ module nanosoc_sysio_apb_ss #(
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
.RXD (uart1_rxd), // Receive data
// .RXD (uart1_rxd), // Receive data
// .TXD (uart1_txd), // Transmit data
// .TXEN (uart1_txen), // Transmit Enabled
// .BAUDTICK (), // Baud rate x16 tick output (for testing)
// USRT1 Interface - From USRT TXD
.TX_VALID_o (usrt1_txd_tvalid),
.TX_DATA8_o (usrt1_txd_tdata),
.TX_READY_i (usrt1_txd_tready),
.TXD (uart1_txd), // Transmit data
.TXEN (uart1_txen), // Transmit Enabled
// USRT1 Interface - To USRT RXD
.RX_VALID_i (usrt1_rxd_tvalid),
.RX_DATA8_i (usrt1_rxd_tdata),
.RX_READY_o (usrt1_rxd_tready),
.BAUDTICK (), // Baud rate x16 tick output (for testing)
.TXINT (uart1_txint), // Transmit Interrupt
.RXINT (uart1_rxint), // Receive Interrupt
......@@ -682,8 +720,11 @@ module nanosoc_sysio_apb_ss #(
assign uart1_prdata = {32{1'b0}};
assign uart1_pready = 1'b1;
assign uart1_pslverr = 1'b0;
assign uart1_txd = 1'b1;
assign uart1_txen = 1'b0;
// assign uart1_txd = 1'b1;
// assign uart1_txen = 1'b0;
assign usrt1_txd_tvalid = 1'b0;
assign usrt1_txd_tdata = {8{1'b0}};
assign usrt1_rxd_tready = 1'b0;
assign uart1_txint = 1'b0;
assign uart1_rxint = 1'b0;
assign uart1_txovrint = 1'b0;
......
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
View file @ 5b1ffaf6
......@@ -49,8 +49,7 @@ module nanosoc_sysio_decode #(
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000,
parameter BASEADDR_ADC = 32'h4002_0000,
parameter BASEADDR_PVT = 32'h4002_1000
parameter BASEADDR_ADC = 32'h4002_0000
)(
// System Address
input wire hsel,
......@@ -63,9 +62,6 @@ module nanosoc_sysio_decode #(
output wire sysctrl_hsel,
`ifdef AMS_PERIPHERALS
output wire adcsys_hsel,
`endif
`ifdef SNPS_PVT_MONITORING
output wire pvtsys_hsel,
`endif
// Default slave
output wire defslv_hsel
......@@ -92,38 +88,21 @@ module nanosoc_sysio_decode #(
`ifdef AMS_PERIPHERALS
assign adcsys_hsel = hsel & (haddr[31:12]==
BASEADDR_ADC[31:12]); // 0x40020000
`endif
`ifdef SNPS_PVT_MONITORING
assign pvtsys_hsel = hsel & (haddr[31:12]==
BASEADDR_PVT[31:12]); // 0x40021000
`endif
// ----------------------------------------------------------
// Default slave decode logic
// ----------------------------------------------------------
`ifdef AMS_PERIPHERALS
`ifdef SNPS_PVT_MONITORING
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | adcsys_hsel | pvtsys_hsel
);
`else
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | adcsys_hsel
);
`endif
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | adcsys_hsel
);
`else
`ifdef SNPS_PVT_MONITORING
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | pvtsys_hsel
);
`else
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel
);
`endif
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel
);
`endif
endmodule
nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
View file @ 5b1ffaf6
......@@ -13,15 +13,8 @@ module nanosoc_ss_debug #(
// System Parameters
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter APB_ADDR_W = 12, // APB Address Width
parameter APB_DATA_W = 32, // APB Data Width
// SoCDebug Parameters
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
parameter [7:0] FT1248_CLKDIV = 8'd03 // Clock Division Ratio
parameter PROMPT_CHAR = "]"
)(
// System Clocks and Resets
input wire SYS_HCLK,
......@@ -42,39 +35,35 @@ module nanosoc_ss_debug #(
input wire [SYS_DATA_W-1:0] DEBUG_HRDATA,
input wire DEBUG_HREADY,
input wire DEBUG_HRESP,
// USRT0 TXD axi byte stream
output wire ADP_RXD_TVALID_o,
output wire [ 7:0] ADP_RXD_TDATA_o ,
input wire ADP_RXD_TREADY_i,
// USRT0 RXD axi byte stream
input wire ADP_TXD_TVALID_i,
input wire [ 7:0] ADP_TXD_TDATA_i ,
output wire ADP_TXD_TREADY_o,
// APB Slave Interface - USRT
input wire DEBUG_PSEL, // Device select
input wire [APB_ADDR_W-1:0] DEBUG_PADDR, // Address
input wire DEBUG_PENABLE, // Transfer control
input wire DEBUG_PWRITE, // Write control
input wire [APB_DATA_W-1:0] DEBUG_PWDATA, // Write data
output wire [APB_DATA_W-1:0] DEBUG_PRDATA, // Read data
output wire DEBUG_PREADY, // Device ready
output wire DEBUG_PSLVERR, // Device error response
// FT1248 Interace - FT1248
output wire FT_CLK_O, // SCLK
output wire FT_SSN_O, // SS_N
input wire FT_MISO_I, // MISO
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
// USRT0 TXD axi byte stream
output wire STD_RXD_TVALID_o,
output wire [ 7:0] STD_RXD_TDATA_o ,
input wire STD_RXD_TREADY_i,
// USRT0 RXD axi byte stream
input wire STD_TXD_TVALID_i,
input wire [ 7:0] STD_TXD_TDATA_i ,
output wire STD_TXD_TREADY_o,
// GPIO interface
output wire [7:0] GPO8,
input wire [7:0] GPI8
);
//---------------------------
// SoCDebug Instantiation
//---------------------------
socdebug_ahb #(
.PROMPT_CHAR(PROMPT_CHAR),
.FT1248_WIDTH(FT1248_WIDTH),
.FT1248_CLKON(FT1248_CLKON),
.FT1248_CLKDIV(FT1248_CLKDIV)
.PROMPT_CHAR(PROMPT_CHAR)
) u_socdebug (
// AHB-lite Master Interface - ADP
.HCLK(SYS_HCLK),
......@@ -91,31 +80,23 @@ module nanosoc_ss_debug #(
.HREADY_i(DEBUG_HREADY),
.HRESP_i(DEBUG_HRESP),
// APB Slave Interface - USRT
.PCLK(SYS_PCLK),
.PCLKG(SYS_PCLKG),
.PRESETn(SYS_PRESETn),
.PSEL_i(DEBUG_PSEL),
.PADDR_i(DEBUG_PADDR[APB_ADDR_W-1:2]),
.PENABLE_i(DEBUG_PENABLE),
.PWRITE_i(DEBUG_PWRITE),
.PWDATA_i(DEBUG_PWDATA),
.PRDATA_o(DEBUG_PRDATA),
.PREADY_o(DEBUG_PREADY),
.PSLVERR_o(DEBUG_PSLVERR),
.ADP_RXD_TVALID_o(ADP_RXD_TVALID_o),
.ADP_RXD_TDATA_o( ADP_RXD_TDATA_o ),
.ADP_RXD_TREADY_i(ADP_RXD_TREADY_i),
.ADP_TXD_TVALID_i(ADP_TXD_TVALID_i),
.ADP_TXD_TDATA_i (ADP_TXD_TDATA_i ),
.ADP_TXD_TREADY_o(ADP_TXD_TREADY_o),
// FT1248 Interace - FT1248
.FT_CLK_O(FT_CLK_O),
.FT_SSN_O(FT_SSN_O),
.FT_MISO_I(FT_MISO_I),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
.STD_RXD_TVALID_o(STD_RXD_TVALID_o),
.STD_RXD_TDATA_o( STD_RXD_TDATA_o ),
.STD_RXD_TREADY_i(STD_RXD_TREADY_i),
.STD_TXD_TVALID_i(STD_TXD_TVALID_i),
.STD_TXD_TDATA_i (STD_TXD_TDATA_i ),
.STD_TXD_TREADY_o(STD_TXD_TREADY_o),
// GPIO interface
.GPO8_o(GPO8),
.GPI8_i(GPI8)
);
endmodule
\ No newline at end of file
endmodule
nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
View file @ 5b1ffaf6
......@@ -118,7 +118,24 @@ module nanosoc_ss_systemctrl #(
input wire CPU_LOCKUP, // Processor status - Locked up
input wire CPU_SLEEPING,
input wire CPU_SLEEPDEEP,
// USRT0 TXD axi byte stream
output wire USRT0_TXD_TVALID,
output wire [ 7:0] USRT0_TXD_TDATA,
input wire USRT0_TXD_TREADY,
// USRT0 RXD axi byte stream
input wire USRT0_RXD_TVALID,
input wire [ 7:0] USRT0_RXD_TDATA,
output wire USRT0_RXD_TREADY,
// USRT1 TXD axi byte stream
output wire USRT1_TXD_TVALID,
output wire [ 7:0] USRT1_TXD_TDATA,
input wire USRT1_TXD_TREADY,
// USRT1 RXD axi byte stream
input wire USRT1_RXD_TVALID,
input wire [ 7:0] USRT1_RXD_TDATA,
output wire USRT1_RXD_TREADY,
// GPIO
input wire [15:0] P0_IN, // GPIO 0 inputs
output wire [15:0] P0_OUT, // GPIO 0 outputs
......@@ -136,12 +153,13 @@ module nanosoc_ss_systemctrl #(
// -------------------------------
wire apbactive;
wire uart0_rxd; // Uart 0 receive data
wire uart0_txd; // Uart 0 transmit data
wire uart0_txen; // Uart 0 transmit data enable
wire uart1_rxd; // Uart 1 receive data
wire uart1_txd; // Uart 1 transmit data
wire uart1_txen; // Uart 1 transmit data enable
// wire uart0_rxd; // Uart 0 receive data
// wire uart0_txd; // Uart 0 transmit data
// wire uart0_txen; // Uart 0 transmit data enable
// wire uart1_rxd; // Uart 1 receive data
// wire uart1_txd; // Uart 1 transmit data
// wire uart1_txen; // Uart 1 transmit data enable
wire uart2_rxd; // Uart 2 receive data
wire uart2_txd; // Uart 2 transmit data
wire uart2_txen; // Uart 2 transmit data enable
......@@ -184,12 +202,12 @@ module nanosoc_ss_systemctrl #(
// -------------------------------
nanosoc_pin_mux u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart0_rxd ( ),
.uart0_txd (1'b1),
.uart0_txen (1'b1),
.uart1_rxd ( ),
.uart1_txd (1'b1),
.uart1_txen (1'b1),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
......@@ -306,12 +324,21 @@ module nanosoc_ss_systemctrl #(
.PMUENABLE(SYS_PMUENABLE),
// IO signaling
.uart0_rxd(uart1_txd), // crossover
.uart0_txd(uart0_txd),
.uart0_txen(uart0_txen),
.uart1_rxd(uart0_txd), // crossover
.uart1_txd(uart1_txd),
.uart1_txen(uart1_txen),
// USRT0
.usrt0_txd_tvalid (USRT0_TXD_TVALID),
.usrt0_txd_tdata (USRT0_TXD_TDATA ),
.usrt0_txd_tready (USRT0_TXD_TREADY),
.usrt0_rxd_tvalid (USRT0_RXD_TVALID),
.usrt0_rxd_tdata (USRT0_RXD_TDATA ),
.usrt0_rxd_tready (USRT0_RXD_TREADY),
// USRT1
.usrt1_txd_tvalid (USRT1_TXD_TVALID),
.usrt1_txd_tdata (USRT1_TXD_TDATA ),
.usrt1_txd_tready (USRT1_TXD_TREADY),
.usrt1_rxd_tvalid (USRT1_RXD_TVALID),
.usrt1_rxd_tdata (USRT1_RXD_TDATA ),
.usrt1_rxd_tready (USRT1_RXD_TREADY),
// UART2
.uart2_rxd(uart2_rxd),
.uart2_txd(uart2_txd),
.uart2_txen(uart2_txen),
......@@ -358,4 +385,4 @@ module nanosoc_ss_systemctrl #(
.HRESP(SYSTABLE_HRESP),
.HREADYOUT(SYSTABLE_HREADYOUT)
);
endmodule
\ No newline at end of file
endmodule
nanosoc/nanosoc_system/verilog/nanosoc_system.v
View file @ 5b1ffaf6
......@@ -63,7 +63,7 @@ module nanosoc_system #(
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
parameter [7:0] FT1248_CLKDIV = 8'd03, // Clock Division Ratio
parameter [7:0] FT1248_CLKDIV = 8'd15, // Clock Division Ratio (4x4 for RP-PIO)
// Address of System ROM Table
parameter SYSTABLE_BASE = 32'hF000_0000, // Base Address of System ROM Table
......@@ -92,31 +92,35 @@ module nanosoc_system #(
output wire CPU_0_SWDO, // SWD data output
output wire CPU_0_SWDOEN, // SWD data output enable
// FT1248 Interace - FT1248
output wire FT_CLK_O, // SCLK
output wire FT_SSN_O, // SS_N
input wire FT_MISO_I, // MISO
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
// GPIO interface
output wire [7:0] GPO8,
input wire [7:0] GPI8,
// GPIO
input wire [15:0] P0_IN, // GPIO 0 inputs
output wire [15:0] P0_OUT, // GPIO 0 outputs
output wire [15:0] P0_OUTEN, // GPIO 0 output enables
output wire [15:0] P0_ALTFUNC, // GPIO 0 alternate function (pin mux)
input wire [15:0] P1_IN, // GPIO 1 inputs
output wire [15:0] P1_OUT, // GPIO 1 outputs
output wire [15:0] P1_OUTEN, // GPIO 1 output enables
output wire [15:0] P1_ALTFUNC, // GPIO 1 alternate function (pin mux)
output wire [15:0] P1_OUT_MUX, // GPIO 1 Output Port Drive
output wire [15:0] P1_OUT_EN_MUX // Active High output drive enable (pad tech dependent)
output wire [15:0] P1_OUTEN // GPIO 1 output enables
);
// system General purpose I/O ports - before NANOSOC specific mappings
wire [15:0] SYS_P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
wire [15:0] SYS_P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
wire [15:0] SYS_P0_IN; // GPIO 0 inputs
wire [15:0] SYS_P0_OUT; // GPIO 0 outputs
wire [15:0] SYS_P0_OUTEN; // GPIO 0 output enables
wire [15:0] SYS_P1_IN; // GPIO 1 inputs
wire [15:0] SYS_P1_OUT; // GPIO 1 outputs
wire [15:0] SYS_P1_OUTEN; // GPIO 1 output enables
wire [15:0] SYS_P1_OUT_MUX; // GPIO 1 Output Port Drive
wire [15:0] SYS_P1_OUT_EN_MUX; // Active High output drive enable (pad tech dependent)
wire FT_CLK_O; // SCLK
wire FT_SSN_O; // SS_N
wire FT_MISO_I; // MISO
wire [FT1248_WIDTH-1:0] FT_MIOSIO_O; // MIOSIO tristate output when enabled
wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate output enable (active hi)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate output enable (active lo)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
//--------------------------
// Local Parameters
//--------------------------
......@@ -165,6 +169,11 @@ module nanosoc_system #(
wire CPU_LOCKUP; // Combined Lockup from CPUs
wire CPU_SLEEPDEEP; // Combined Sleepdeep from CPUs
wire CPU_SLEEPING; // Combined sleeping from CPUs
// ADP GPIO interface
wire [7:0] ADP_GPO8;
wire [7:0] ADP_GPI8 = ADP_GPO8;
//--------------------------
// CPU Subsystem
......@@ -646,11 +655,49 @@ module nanosoc_system #(
// Reset Request Wiring
//--------------------------
assign DEBUG_RESETREQ = GPO8[0];
assign DEBUG_RESETREQ = ADP_GPO8[0];
// USRT0 TXD axi byte stream
wire USRT0_TXD_TVALID;
wire [ 7:0] USRT0_TXD_TDATA ;
wire USRT0_TXD_TREADY;
// USRT0 RXD axi byte stream
wire USRT0_RXD_TVALID;
wire [ 7:0] USRT0_RXD_TDATA ;
wire USRT0_RXD_TREADY;
// USRT1 TXD axi byte stream
wire USRT1_TXD_TVALID;
wire [ 7:0] USRT1_TXD_TDATA ;
wire USRT1_TXD_TREADY;
// USRT1 RXD axi byte stream
wire USRT1_RXD_TVALID;
wire [ 7:0] USRT1_RXD_TDATA ;
wire USRT1_RXD_TREADY;
wire ADP_RXD_TVALID;
wire [ 7:0] ADP_RXD_TDATA ;
wire ADP_RXD_TREADY;
wire ADP_TXD_TVALID;
wire [ 7:0] ADP_TXD_TDATA ;
wire ADP_TXD_TREADY;
// STDIN to ADP controller
wire STD_RXD_TVALID;
wire [ 7:0] STD_RXD_TDATA;
wire STD_RXD_TREADY;
// STDOUT to ADP controller
wire STD_TXD_TVALID;
wire [ 7:0] STD_TXD_TDATA;
wire STD_TXD_TREADY;
wire FT1248MODE = P1_IN[7]; // added to support EXTIO mapping
// Sideband Wiring
//--------------------------
wire [7:0] FT_CLKDIV;
assign FT_CLKDIV = FT1248_CLKDIV;
assign CPU_0_RXEV = DMAC_ANY_DONE;
// Instantiate Subsystem
......@@ -659,16 +706,8 @@ module nanosoc_system #(
// System Parameters
.SYS_ADDR_W(SYS_ADDR_W),
.SYS_DATA_W(SYS_DATA_W),
// APB Parameters
.APB_ADDR_W(APB_ADDR_W),
.APB_DATA_W(APB_DATA_W),
// SoCDebug Parameters
.PROMPT_CHAR(PROMPT_CHAR),
.FT1248_WIDTH(FT1248_WIDTH),
.FT1248_CLKON(FT1248_CLKON),
.FT1248_CLKDIV(FT1248_CLKDIV)
.PROMPT_CHAR(PROMPT_CHAR)
) u_ss_debug (
// System Clocks and Resets
.SYS_HCLK(SYS_HCLK),
......@@ -690,28 +729,113 @@ module nanosoc_system #(
.DEBUG_HREADY(DEBUG_HREADY),
.DEBUG_HRESP(DEBUG_HRESP),
// APB Slave Interface - USRT
.DEBUG_PSEL(DEBUG_PSEL),
.DEBUG_PADDR(SYSIO_PADDR),
.DEBUG_PENABLE(SYSIO_PENABLE),
.DEBUG_PWRITE(SYSIO_PWRITE),
.DEBUG_PWDATA(SYSIO_PWDATA),
.DEBUG_PRDATA(DEBUG_PRDATA),
.DEBUG_PREADY(DEBUG_PREADY),
.DEBUG_PSLVERR(DEBUG_PSLVERR),
// FT1248 Interface - FT1248
.FT_CLK_O(FT_CLK_O),
.FT_SSN_O(FT_SSN_O),
.FT_MISO_I(FT_MISO_I),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
.ADP_RXD_TVALID_o(ADP_RXD_TVALID),
.ADP_RXD_TDATA_o( ADP_RXD_TDATA ),
.ADP_RXD_TREADY_i(ADP_RXD_TREADY),
.ADP_TXD_TVALID_i(ADP_TXD_TVALID),
.ADP_TXD_TDATA_i (ADP_TXD_TDATA ),
.ADP_TXD_TREADY_o(ADP_TXD_TREADY),
.STD_RXD_TVALID_o(STD_RXD_TVALID),
.STD_RXD_TDATA_o( STD_RXD_TDATA ),
.STD_RXD_TREADY_i(STD_RXD_TREADY),
.STD_TXD_TVALID_i(STD_TXD_TVALID),
.STD_TXD_TDATA_i (STD_TXD_TDATA ),
.STD_TXD_TREADY_o(STD_TXD_TREADY),
// GPIO interface
.GPO8(GPO8),
.GPI8(GPI8)
.GPO8(ADP_GPO8),
.GPI8(ADP_GPI8)
);
// Instantiation of USRT Controller
socdebug_usrt_control u_usrt_control (
// APB Clock and Reset Signals
.PCLK (SYS_PCLK),
.PCLKG (SYS_PCLKG), // Gated PCLK for bus
.PRESETn (SYS_PRESETn),
// APB Interface Signals
.PSEL (DEBUG_PSEL),
.PADDR (SYSIO_PADDR[11:2]),
.PENABLE (SYSIO_PENABLE),
.PWRITE (SYSIO_PWRITE),
.PWDATA (SYSIO_PWDATA),
.PRDATA (DEBUG_PRDATA),
.PREADY (DEBUG_PREADY),
.PSLVERR (DEBUG_PSLVERR),
.ECOREVNUM (4'h0),
// ADP Interface - From USRT to ADP
.TX_VALID_o (STD_TXD_TVALID),
.TX_DATA8_o (STD_TXD_TDATA ),
.TX_READY_i (STD_TXD_TREADY),
// ADP Interface - From ADP to USRT
.RX_VALID_i (STD_RXD_TVALID),
.RX_DATA8_i (STD_RXD_TDATA ),
.RX_READY_o (STD_RXD_TREADY),
// Interrupt Interfaces
.TXINT ( ), // Transmit Interrupt
.RXINT ( ), // Receive Interrupt
.TXOVRINT ( ), // Transmit Overrun Interrupt
.RXOVRINT ( ), // Receive Overrun Interrupt
.UARTINT ( ) // Combined Interrupt
);
wire FT_ADP_RXD_TVALID ;
wire [7:0] FT_ADP_RXD_TDATA ;
wire FT_ADP_RXD_TREADY ;
wire FT_ADP_TXD_TVALID ;
wire [7:0] FT_ADP_TXD_TDATA ;
wire FT_ADP_TXD_TREADY ;
wire EXT_ADP_RXD_TVALID ;
wire [7:0] EXT_ADP_RXD_TDATA ;
wire EXT_ADP_RXD_TREADY ;
wire EXT_ADP_TXD_TVALID ;
wire [7:0] EXT_ADP_TXD_TDATA ;
wire EXT_ADP_TXD_TREADY ;
wire EXT_DAT_RXD_TVALID ;
wire [7:0] EXT_DAT_RXD_TDATA ;
wire EXT_DAT_RXD_TREADY ;
wire EXT_DAT_TXD_TVALID ;
wire [7:0] EXT_DAT_TXD_TDATA ;
wire EXT_DAT_TXD_TREADY ;
/// See the AXI stream muxes by EXTIO interface (below)
// Instantiation of FT1248 Controller
socdebug_ft1248_control #(
.FT1248_WIDTH (FT1248_WIDTH),
.FT1248_CLKON (FT1248_CLKON)
) u_ft1248_control (
.clk (SYS_HCLK),
.resetn (SYS_HRESETn),
.ft_clkdiv (FT_CLKDIV),
.ft_clk_o (FT_CLK_O),
.ft_ssn_o (FT_SSN_O),
.ft_miso_i (FT_MISO_I),
.ft_miosio_o (FT_MIOSIO_O),
.ft_miosio_e (FT_MIOSIO_E),
.ft_miosio_z (FT_MIOSIO_Z),
.ft_miosio_i (FT_MIOSIO_I),
// ADP Interface - FT1248 to ADP
.txd_tvalid (FT_ADP_TXD_TVALID),
.txd_tdata (FT_ADP_TXD_TDATA ),
.txd_tready (FT_ADP_TXD_TREADY),
.txd_tlast ( ),
// ADP Interface - FT_ADP to FT1248
.rxd_tvalid (FT_ADP_RXD_TVALID),
.rxd_tdata (FT_ADP_RXD_TDATA ),
.rxd_tready (FT_ADP_RXD_TREADY),
.rxd_tlast (1'b0)
);
//--------------------------
......@@ -1083,29 +1207,183 @@ module nanosoc_system #(
.CPU_LOCKUP(CPU_LOCKUP),
.CPU_SLEEPING(CPU_SLEEPING),
.CPU_SLEEPDEEP(CPU_SLEEPDEEP),
// USRT0
.USRT0_TXD_TVALID (USRT0_TXD_TVALID),
.USRT0_TXD_TDATA (USRT0_TXD_TDATA ),
.USRT0_TXD_TREADY (USRT0_TXD_TREADY),
.USRT0_RXD_TVALID (USRT0_RXD_TVALID),
.USRT0_RXD_TDATA (USRT0_RXD_TDATA ),
.USRT0_RXD_TREADY (USRT0_RXD_TREADY),
// USRT1
.USRT1_TXD_TVALID (USRT1_TXD_TVALID),
.USRT1_TXD_TDATA (USRT1_TXD_TDATA ),
.USRT1_TXD_TREADY (USRT1_TXD_TREADY),
.USRT1_RXD_TVALID (USRT1_RXD_TVALID),
.USRT1_RXD_TDATA (USRT1_RXD_TDATA ),
.USRT1_RXD_TREADY (USRT1_RXD_TREADY),
// GPIO
.P0_IN(P0_IN),
.P0_OUT(P0_OUT),
.P0_OUTEN(P0_OUTEN),
.P0_ALTFUNC(P0_ALTFUNC),
.P1_IN(P1_IN),
.P1_OUT(P1_OUT),
.P1_OUTEN(P1_OUTEN),
.P1_ALTFUNC(P1_ALTFUNC),
.P1_OUT_MUX(P1_OUT_MUX),
.P1_OUT_EN_MUX(P1_OUT_EN_MUX)
.P0_IN (SYS_P0_IN),
.P0_OUT (SYS_P0_OUT),
.P0_OUTEN (SYS_P0_OUTEN),
.P0_ALTFUNC (SYS_P0_ALTFUNC),
.P1_IN (SYS_P1_IN),
.P1_OUT (SYS_P1_OUT),
.P1_OUTEN (SYS_P1_OUTEN),
.P1_ALTFUNC (SYS_P1_ALTFUNC),
.P1_OUT_MUX (SYS_P1_OUT_MUX),
.P1_OUT_EN_MUX (SYS_P1_OUT_EN_MUX)
);
// ADP input routing
assign ADP_RXD_TREADY = (FT1248MODE) ? FT_ADP_RXD_TREADY : EXT_ADP_RXD_TREADY;
assign ADP_TXD_TVALID = (FT1248MODE) ? FT_ADP_TXD_TVALID : EXT_ADP_TXD_TVALID;
assign ADP_TXD_TDATA = (FT1248MODE) ? FT_ADP_TXD_TDATA : EXT_ADP_TXD_TDATA;
// FT1248 ADP output routing
assign FT_ADP_RXD_TVALID = (FT1248MODE) ? ADP_RXD_TVALID : 1'b0;
assign FT_ADP_RXD_TDATA = (FT1248MODE) ? ADP_RXD_TDATA : 8'b00000000;
assign FT_ADP_TXD_TREADY = (FT1248MODE) ? ADP_TXD_TREADY : 1'b0;
// EXTIO ADP output routing
assign EXT_ADP_RXD_TVALID = (FT1248MODE) ? 1'b0 : ADP_RXD_TVALID;
assign EXT_ADP_RXD_TDATA = (FT1248MODE) ? 8'b00000000 : ADP_RXD_TDATA;
assign EXT_ADP_TXD_TREADY = (FT1248MODE) ? 1'b0 : ADP_TXD_TREADY;
// USRT0 input loopback test - or disable
assign USRT0_RXD_TVALID = (FT1248MODE) ? USRT1_TXD_TVALID : 1'b0;
assign USRT0_RXD_TDATA = (FT1248MODE) ? USRT1_TXD_TDATA : 8'b00000000;
assign USRT0_TXD_TREADY = (FT1248MODE) ? USRT1_RXD_TREADY : 1'b0;
// USRT1 input loopback - or EXT DAT
assign USRT1_RXD_TVALID = (FT1248MODE) ? USRT0_TXD_TVALID : EXT_DAT_TXD_TVALID ;
assign USRT1_RXD_TDATA = (FT1248MODE) ? USRT0_TXD_TDATA : EXT_DAT_TXD_TDATA;
assign USRT1_TXD_TREADY = (FT1248MODE) ? USRT0_RXD_TREADY : EXT_DAT_RXD_TREADY;
// EXT DAT RXD
assign EXT_DAT_RXD_TVALID = (FT1248MODE) ? 1'b0 : USRT1_TXD_TVALID;
assign EXT_DAT_RXD_TDATA = (FT1248MODE) ? 8'b00000000 : USRT1_TXD_TDATA ;
assign EXT_DAT_TXD_TREADY = (FT1248MODE) ? 1'b0 : USRT1_RXD_TREADY;
wire [3:0] iodata4_i;
wire [3:0] iodata4_o;
wire [3:0] iodata4_e;
wire [3:0] iodata4_t;
wire ioreq1_o;
wire ioreq2_o;
wire ioack_i ;
extio8x4_axis_initiator u_extio8x4_axis_initiator
(
.clk ( SYS_HCLK ),
.resetn ( SYS_HRESETn ),
.testmode ( SYS_TESTMODE ),
// RX 4-channel AXIS interface
.axis_rx0_tvalid ( EXT_ADP_RXD_TVALID ),
.axis_rx0_tdata8 ( EXT_ADP_RXD_TDATA ),
.axis_rx0_tready ( EXT_ADP_RXD_TREADY ),
.axis_rx1_tvalid ( EXT_DAT_RXD_TVALID ),
.axis_rx1_tdata8 ( EXT_DAT_RXD_TDATA ),
.axis_rx1_tready ( EXT_DAT_RXD_TREADY ),
.axis_tx0_tvalid ( EXT_ADP_TXD_TVALID ),
.axis_tx0_tdata8 ( EXT_ADP_TXD_TDATA ),
.axis_tx0_tready ( EXT_ADP_TXD_TREADY ),
.axis_tx1_tvalid ( EXT_DAT_TXD_TVALID ),
.axis_tx1_tdata8 ( EXT_DAT_TXD_TDATA ),
.axis_tx1_tready ( EXT_DAT_TXD_TREADY ),
// external io interface
.iodata4_a ( iodata4_i ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_o ( ioreq1_o ),
.ioreq2_o ( ioreq2_o ),
.ioack_a ( ioack_i )
);
// --------------------------------------------------------------------------------
// EXTIO8x4 stream interface - enabled when P1[7] input is low
// default in previous testbenches was pullup (for FT1248, UART2)
//
// v1 mapping was: v2 config
// P1[0] - ft_miso_in ioreq1_o
// P1[1] - ft_clk_out ioreq2_o
// P1[2] - ft_miosio_io ioack_i
// P1[3] - ft_ssn_out iodata[0]
// P1[4] - uart2_rxd iodata[1]
// P1[5] - uart2_txd iodata[2]
// P1[6] - reserved (pullup) iodata[3]
// P1[7] - reserved (pullup) 1'b0
// --------------------------------------------------------------------------------
// SOC specific IO mapping - PORT0
assign SYS_P0_IN[15:0] = P0_IN[15:0];
assign P0_OUT[15:0] = SYS_P0_OUT[15:0];
assign P0_OUTEN[15:0] = SYS_P0_OUTEN[15:0];
// PORT 1 [7] - low for EXTIO, high for FT1248/UART2
// reassign PORT1[3:0] to FT1248x1 interface
assign FT_MISO_I = (FT1248MODE) ? P1_IN[0] : 1'b0; // FT_MISO INPUT pad configuration
assign P1_OUTEN[0] = (FT1248MODE) ? 1'b0 : 1'b1; // IOREQ1 output
assign P1_OUT[0] = (FT1248MODE) ? 1'b0 : ioreq1_o;
assign SYS_P1_IN[0] = (FT1248MODE) ? 1'b0 : ioreq1_o; // P1_IN[0]
assign P1_OUT[1] = (FT1248MODE) ? FT_CLK_O : ioreq2_o; // FT_CLK OUTPUT pad configuration
assign P1_OUTEN[1] = (FT1248MODE) ? 1'b1 : 1'b1;
assign SYS_P1_IN[1] = (FT1248MODE) ? 1'b0 : ioreq2_o; // P1_IN[1]
assign FT_MIOSIO_I[0] = (FT1248MODE) ? P1_IN[2] : 1'b0; // FT_MIOSIO INOUT pad configuration
assign P1_OUT[2] = (FT1248MODE) ? FT_MIOSIO_O[0] : 1'b0;
assign P1_OUTEN[2] = (FT1248MODE) ? FT_MIOSIO_E[0] : 1'b0;
assign SYS_P1_IN[2] = (FT1248MODE) ? 1'b0 : P1_IN[2]; // P1_IN[2];
assign ioack_i = (FT1248MODE) ? 1'b1 : P1_IN[2];
assign P1_OUT[3] = (FT1248MODE) ? FT_SSN_O : iodata4_o[0]; // FT_SSN OUTPUT pad configuration
assign P1_OUTEN[3] = (FT1248MODE) ? 1'b1 : iodata4_e[0];
assign SYS_P1_IN[3] = (FT1248MODE) ? 1'b1 : P1_IN[3];
assign iodata4_i[0] = (FT1248MODE) ? 1'b1 : P1_IN[3];
assign P1_OUT[4] = (FT1248MODE) ? SYS_P1_OUT_MUX[4] : iodata4_o[1];
assign P1_OUTEN[4] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[4] : iodata4_e[1];
assign SYS_P1_IN[4] = (FT1248MODE) ? P1_IN[4] : SYS_P1_OUT_MUX[5];
assign iodata4_i[1] = (FT1248MODE) ? 1'b1 : P1_IN[4];
assign P1_OUT[5] = (FT1248MODE) ? SYS_P1_OUT_MUX[5] : iodata4_o[2];
assign P1_OUTEN[5] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[5] : iodata4_e[2];
assign SYS_P1_IN[5] = P1_IN[5];
assign iodata4_i[2] = (FT1248MODE) ? 1'b1 : P1_IN[5];
assign P1_OUT[6] = (FT1248MODE) ? SYS_P1_OUT_MUX[6] : iodata4_o[3];
assign P1_OUTEN[6] = (FT1248MODE) ? SYS_P1_OUT_EN_MUX[6] : iodata4_e[3];
assign SYS_P1_IN[6] = P1_IN[6];
assign iodata4_i[3] = (FT1248MODE) ? 1'b1 : P1_IN[6];
assign P1_OUT[7] = SYS_P1_OUT_MUX[7];
assign P1_OUTEN[7] = SYS_P1_OUT_EN_MUX[7];
assign SYS_P1_IN[7] = P1_IN[7];
// the rest of PORT1[3:0] is GPIO/AltFunction
assign SYS_P1_IN[15:8] = P1_IN[15:8];
assign P1_OUT[15:8] = SYS_P1_OUT_MUX[15:8];
assign P1_OUTEN[15:8] = SYS_P1_OUT_EN_MUX[15:8];
//--------------------------
// Interrupt Wiring
//--------------------------
assign CPU_0_IRQ [3:0] = EXP_IRQ [3:0];
assign CPU_0_IRQ [ 3: 0] = SYS_APB_IRQ[ 3: 0]; // nanansocv1: EXP_IRQ[3:0];
assign CPU_0_IRQ [ 5: 4] = SYS_APB_IRQ[ 5: 4];
assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | SYS_GPIO0_ANY_IRQ;
assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | SYS_GPIO1_ANY_IRQ;
assign CPU_0_IRQ [14: 8] = SYS_APB_IRQ[14: 8];
assign CPU_0_IRQ [10: 8] = SYS_APB_IRQ[10: 8];
assign CPU_0_IRQ [14:11] = EXP_IRQ[3:0]; // nanosocv1: SYS_APB_IRQ[14:11];
assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16] | SYS_GPIO0_IRQ[15:0];
......@@ -1303,4 +1581,4 @@ module nanosoc_system #(
.SYSTABLE_HREADYMUX(SYSTABLE_HREADY)
);
endmodule
\ No newline at end of file
endmodule
socdebug_tech @ 05781fa3
Compare 7572912a...05781fa3
Subproject commit 7572912a3cde67880b0579db6f2e970ebaf2002d
Subproject commit 05781fa353a8918c8206e9cc10b7e8aaef5203aa
software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
View file @ 5b1ffaf6
......@@ -77,10 +77,10 @@ typedef enum IRQn
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *********************************************************/
EXP0_IRQn = 0, /*!< was UARTRX0_IRQn Interrupt */
EXP1_IRQn = 1, /*!< was UARTTX0_IRQn Interrupt */
EXP2_IRQn = 2, /*!< was UARTRX1_IRQn Interrupt */
EXP3_IRQn = 3, /*!< was UARTTX1_IRQn Interrupt */
UARTRX0_IRQn = 0, /*!< was UARTRX0_IRQn Interrupt */
UARTTX0_IRQn = 1, /*!< was UARTTX0_IRQn Interrupt */
UARTRX1_IRQn = 2, /*!< was UARTRX1_IRQn Interrupt */
UARTTX1_IRQn = 3, /*!< was UARTTX1_IRQn Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
......@@ -88,10 +88,10 @@ typedef enum IRQn
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
EXPB_IRQn = 11, /*!< was IRQ11 - Unused */
EXPC_IRQn = 12, /*!< was UART 0 Overflow Interrupt */
EXPD_IRQn = 13, /*!< was UART 1 Overflow Interrupt */
UARTOVF2_IRQn = 14, /*!< UART 2 Overflow Interrupt */
EXP0_IRQn = 11, /*!< was IRQ11 - Unused */
EXP1_IRQn = 12, /*!< was UART 0 Overflow Interrupt */
EXP2_IRQn = 13, /*!< was UART 1 Overflow Interrupt */
EXP3_IRQn = 14, /*!< UART 2 Overflow Interrupt */
DMA_IRQn = 15, /*!< PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
......
software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
View file @ 5b1ffaf6
......@@ -76,10 +76,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD EXP0_Handler ; was: UARTRX0_Handler
DCD EXP1_Handler ; was: UARTTX0_Handler
DCD EXP2_Handler ; was: UARTRX1_Handler
DCD EXP3_Handler ; was: UARTTX1_Handler
DCD UARTRX0_Handler ; UARTRX0_Handler was: EXPA_Handler
DCD UARTTX0_Handler ; UARTTX0_Handler was: EXPB_Handler
DCD UARTRX1_Handler ; UARTRX1_Handler was: EXPC_Handler
DCD UARTTX1_Handler ; UARTTX1_Handler was: EXPD_Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
......@@ -87,10 +87,10 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD EXPB_Handler ; was: Reserved
DCD EXPC_Handler ; was: UARTOVF0_Handler Overflow Handler
DCD EXPD_Handler ; was: UARTOVF1_Handler Overflow Handler
DCD UARTOVF2_Handler ; UART 2 Overflow Handler
DCD EXP0_Handler ; was: Reserved
DCD EXP1_Handler ; was: UARTOVF0_Handler Overflow Handler
DCD EXP2_Handler ; was: UARTOVF1_Handler Overflow Handler
DCD EXP3_Handler ; was: UART 2 Overflow Handler
DCD DMA_Handler ; DMA handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
......@@ -152,10 +152,10 @@ SysTick_Handler PROC
B .
ENDP
Default_Handler PROC
EXPORT EXP0_Handler [WEAK]
EXPORT EXP1_Handler [WEAK]
EXPORT EXP2_Handler [WEAK]
EXPORT EXP3_Handler [WEAK]
EXPORT UARTRX0_Handler [WEAK]
EXPORT UARTTX0_Handler [WEAK]
EXPORT UARTRX1_Handler [WEAK]
EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
......@@ -163,10 +163,10 @@ Default_Handler PROC
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT EXPB_Handler [WEAK]
EXPORT EXPC_Handler [WEAK]
EXPORT EXPD_Handler [WEAK]
EXPORT UARTOVF2_Handler [WEAK]
EXPORT EXP0_Handler [WEAK]
EXPORT EXP1_Handler [WEAK]
EXPORT EXP2_Handler [WEAK]
EXPORT EXP3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
......@@ -184,10 +184,14 @@ Default_Handler PROC
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
EXP0_Handler
EXP1_Handler
EXP2_Handler
EXP3_Handler
;EXP0_Handler
;EXP1_Handler
;EXP2_Handler
;EXP3_Handler
UARTRX0_Handler
UARTTX0_Handler
UARTRX1_Handler
UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
......@@ -195,9 +199,10 @@ PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
EXPB_Handler
EXPC_Handler
EXPD_Handler
EXP0_Handler
EXP1_Handler
EXP2_Handler
EXP3_Handler
UARTOVF2_Handler
DMA_Handler
PORT0_0_Handler
......
software/common/bootloader/bootloader.c
View file @ 5b1ffaf6
......@@ -73,7 +73,6 @@ unsigned char UartPutc(unsigned char my_ch)
// return (my_ch);
while (((CMSDK_USRT2->STATE & 1)==1) && ((CMSDK_UART2->STATE & 1)==1)); // Wait if both Transmit Holding registers full
if ((CMSDK_USRT2->STATE & 1)==0) CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
if ((CMSDK_UART2->STATE & 1)==0) CMSDK_UART2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Uart string output
......
software/common/demos/interrupt_demo.c
View file @ 5b1ffaf6
......@@ -162,13 +162,13 @@ void UartExample(void)
// Ensure Interrupt is not pending
NVIC_ClearPendingIRQ(EXP1_IRQn); // NVIC_ClearPendingIRQ(UARTTX0_IRQn);
NVIC_ClearPendingIRQ(EXP2_IRQn); // NVIC_ClearPendingIRQ(UARTRX1_IRQn);
NVIC_ClearPendingIRQ(UARTTX1_IRQn);
NVIC_ClearPendingIRQ(UARTRX1_IRQn);
// Enable Interrupts
NVIC_EnableIRQ(EXP1_IRQn); // NVIC_EnableIRQ(UARTTX0_IRQn);
NVIC_EnableIRQ(EXP2_IRQn); // NVIC_EnableIRQ(UARTRX1_IRQn);
NVIC_EnableIRQ(UARTTX1_IRQn);
NVIC_EnableIRQ(UARTRX1_IRQn);
/* Initialize UART in cross over configuration
uint32_t CMSDK_uart_init(CMSDK_UART_TypeDef *CMSDK_UART,
......@@ -184,8 +184,8 @@ void UartExample(void)
UART #0 - transmit
UART #1 - receive
*/
CMSDK_uart_init(CMSDK_UART0, 0x200, 1, 0, 1, 0, 0, 0);
CMSDK_uart_init(CMSDK_UART1, 0x200, 0, 1, 0, 1, 0, 0);
// CMSDK_uart_init(CMSDK_UART0, 0x200, 1, 0, 1, 0, 0, 0);
CMSDK_uart_init(CMSDK_UART1, 0x200, 1, 1, 1, 1, 0, 0);
rx_count = 0;
tx_count = 0;
......@@ -194,7 +194,7 @@ void UartExample(void)
/* Start first character transfer */
tx_count++;
CMSDK_uart_SendChar(CMSDK_UART0, str_tx[0]); // send the character
CMSDK_uart_SendChar(CMSDK_UART1, str_tx[0]); // send the character
/* The rest of the transfers are handled by interrupts */
while(transmission_complete==0) // loop until transmission completed
......@@ -206,8 +206,8 @@ void UartExample(void)
printf ("Received message : %s\n", str_rx);
NVIC_DisableIRQ(EXP1_IRQn); // NVIC_DisableIRQ(UARTTX0_IRQn); -disable both UART0 TX and UART1 RX IRQs
NVIC_DisableIRQ(EXP2_IRQn); // NVIC_DisableIRQ(UARTRX1_IRQn);
NVIC_DisableIRQ(UARTTX1_IRQn); //-disable both UART1 TX and UART1 RX IRQs
NVIC_DisableIRQ(UARTRX1_IRQn);
return;
}
......@@ -403,23 +403,23 @@ else
// Handlers
// ----------------------------------------------------------
// ---------------------------------
// UART 0 Interrupt service routines
// UART 1 TX Interrupt service routines
// ---------------------------------
//
void UARTTX0_Handler(void)
void UARTTX1_Handler(void)
{
CMSDK_uart_ClearTxIRQ(CMSDK_UART0); // clear TX IRQ
CMSDK_uart_ClearTxIRQ(CMSDK_UART1); // clear TX IRQ
// If the message output is not finished, output next character
if (tx_count < uart_str_length) {
CMSDK_uart_SendChar(CMSDK_UART0,str_tx[tx_count]);
CMSDK_uart_SendChar(CMSDK_UART1,str_tx[tx_count]);
tx_count++;
}
}
// ---------------------------------
// UART 1 Interrupt service routines
// UART 1 RX Interrupt service routines
// ---------------------------------
void UARTRX1_Handler(void)
......