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  • soclabs/nanosoc_tech
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ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
View file @ 2dc8b4aa
...@@ -2,7 +2,7 @@ set_cpf_version 1.1 ...@@ -2,7 +2,7 @@ set_cpf_version 1.1
set_design nanosoc_chip_pads set_design nanosoc_chip_pads
create_power_domain -name TOP -default create_power_domain -name TOP -default
create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08 create_nominal_condition -name nom -voltage 1.08
......
ASIC/44pin/Cadence/scripts/design_import.tcl
View file @ 2dc8b4aa
...@@ -22,16 +22,17 @@ set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tp ...@@ -22,16 +22,17 @@ set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tp
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE # !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs ### Reading LEFs
read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${ROM_LEF}] read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
### Reading Netlist ### Reading Netlist
read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
### Read DEF scan chain ### Read DEF scan chain
#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
### Initializing the Design ### Initializing the Design
init_design init_design
...@@ -39,9 +40,9 @@ init_design ...@@ -39,9 +40,9 @@ init_design
### Adjusting the GUI ### Adjusting the GUI
gui_fit gui_fit
ungroup u_nanosoc_chip_u_system #ungroup u_nanosoc_chip_u_system
create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 150.0 150.0 150.0 150.0 create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 140.0 140.0 140.0 140.0
read_power_intent -cpf ../cpf/nanosoc_imp.cpf read_power_intent -cpf ../cpf/nanosoc_imp.cpf
......
ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl 0 → 100644
View file @ 2dc8b4aa
#########################################
# File : Design Import Logic
# Date : 22nd May 2022
# Author : Srimanth Tenneti
# Description : MMMC + Design Import
#########################################
### Settting PG Nets
set_db init_power_nets {VDD VDDIO VDDACC}
set_db init_ground_nets {VSS VSSIO}
### Processing MMMC
read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs
read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
### Reading Netlist
read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v
### Initializing the Design
init_design
### Adjusting the GUI
gui_fit
#ungroup u_nanosoc_chip_u_system
create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 140.0 140.0 140.0 140.0
read_power_intent -cpf ../cpf/nanosoc_imp.cpf
ASIC/44pin/Cadence/scripts/genus.tcl
View file @ 2dc8b4aa
...@@ -13,52 +13,66 @@ ...@@ -13,52 +13,66 @@
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
## -- Setup libraries -- ## ## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/" set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
set RF_08K rf_08k_ss_1p08v_1p08v_125c.lib
set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
create_library_domain domain1 create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER" set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $RF_08K $ROM_LIB $IO_PAD_DRIVER"
# set_dont_touch SDFF*
check_library > syn_lib_check.log
## -- Load power intent for top and accelerator power domains -- ## ## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ## ## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none #set_db auto_ungroup none
## -- Read in RTL and elaborate top level ## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
elaborate nanosoc_chip_pads elaborate nanosoc_chip_pads
# Preserve hierarchy for M0.
# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
## -- Apply power intent and check library and CPF -- ## ## -- Apply power intent and check library and CPF -- ##
apply_power_intent apply_power_intent
check_library > syn_lib_check.log check_cpf -license lpgxl > syn_cpf_check.log
check_cpf > syn_cpf_check.log
commit_power_intent commit_power_intent
check_power_structure -license lpgxl > syn_pow_check.log check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ## ## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
#set_db dft_scan_style muxed_scan
#set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 1
#read_dft_abstract_model nanosoc_dft_abstract_model
#define_test_signal -name TEST -active high -function test_mode -index 0 TEST
#define_test_signal -name SWDCK -active high -function scan_clock -index 0 SWDCK
#define_test_signal -name NRST -active low -function async_set_reset -index 0 NRST
#define_test_signal -name SWDIO -active high -function shift_enable -default -index 0 SWDIO
#define_test_signal -name CLK -active high -function test_clock -index 0 CLK
#define_scan_chain -name chain_ACCEL -sdi DFT_SDI_1 -sdo DFT_SDO_1 -shared_output
#define_scan_chain -name chain_TOP -sdi DFT_SDI_2 -sdo DFT_SDO_2 -shared_output
#check_dft_rules
#fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin SWDCK
set_db dft_scan_style muxed_scan
set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 4
set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
define_test_signal -name TEST -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
define_test_signal -name CLK -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
define_test_signal -name NRST -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
define_test_signal -name SWDCK -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SWDCK
define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
define_scan_chain -name chain_TOP_3 -sdi P0[3] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[3] -sdo P1[3] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[3] -shared_output -shared_input
fix_pad_cfg -mode input -test_control TEST P0[0]
fix_pad_cfg -mode input -test_control TEST P0[1]
fix_pad_cfg -mode input -test_control TEST P0[2]
fix_pad_cfg -mode input -test_control TEST P0[3]
fix_pad_cfg -mode output -test_control TEST P1[0]
fix_pad_cfg -mode output -test_control TEST P1[1]
fix_pad_cfg -mode output -test_control TEST P1[2]
fix_pad_cfg -mode output -test_control TEST P1[3]
check_dft_rules
fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin CLK
fix_dft_violations -test_control TEST -async_set
set_db syn_generic_effort high set_db syn_generic_effort high
set_db syn_map_effort high set_db syn_map_effort high
...@@ -66,10 +80,8 @@ set_db syn_map_effort high ...@@ -66,10 +80,8 @@ set_db syn_map_effort high
syn_generic syn_generic
syn_map syn_map
#convert_to_scan convert_to_scan
connect_scan_chains
#connect_scan_chains -chains chain_ACCEL -power_domain ACCEL -incremental
#connect_scan_chains -chains chain_TOP -power_domain TOP -incremental
syn_opt syn_opt
...@@ -84,12 +96,11 @@ write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chi ...@@ -84,12 +96,11 @@ write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chi
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
#write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_44pin
#write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_44pin
#write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_44pin
write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_44pin
write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
ASIC/44pin/Cadence/scripts/genus_nodft.tcl 0 → 100644
View file @ 2dc8b4aa
#-----------------------------------------------------------------------------
# NanoSoC gate synthesis script for Cadence Genus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# run: genus -f genus.tcl
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
set RF_08K rf_08k_ss_1p08v_1p08v_125c.lib
set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $RF_08K $ROM_LIB $IO_PAD_DRIVER"
# set_dont_touch SDFF*
check_library > syn_lib_check.log
## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none
## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
elaborate nanosoc_chip_pads
# Preserve hierarchy for M0.
# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
## -- Apply power intent and check library and CPF -- ##
apply_power_intent
check_cpf -license lpgxl > syn_cpf_check.log
commit_power_intent
check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
set_db syn_generic_effort high
set_db syn_map_effort high
syn_generic
syn_map
syn_opt
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_area_44pin.rep
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_timing_44pin.rep
report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_gates_44pin.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_power_44pin.rep
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v
write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.vp
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
ASIC/44pin/Cadence/scripts/nanosoc.mmmc
View file @ 2dc8b4aa
...@@ -2,19 +2,20 @@ set phys_lib /research/AAA/phys_ip_library ...@@ -2,19 +2,20 @@ set phys_lib /research/AAA/phys_ip_library
set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0 set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0 set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_16k/ set ram_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_16k/
set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/ set ram_08k_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_08k/
set rom_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/bootrom/
set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
create_library_set -name default_libset_max\ create_library_set -name default_libset_max\
-timing\ -timing\
[list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${ram_08k_path}/rf_08k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
-si\ -si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB] [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
create_library_set -name default_libset_min\ create_library_set -name default_libset_min\
-timing\ -timing\
[list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${ram_08k_path}/rf_08k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
-si\ -si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB] [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
......
ASIC/44pin/Cadence/scripts/place_macros.tcl
View file @ 2dc8b4aa
...@@ -11,21 +11,21 @@ ...@@ -11,21 +11,21 @@
# relative floorplan # relative floorplan
gui_set_draw_view fplan gui_set_draw_view fplan
delete_relative_floorplan -all delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500} move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6} update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420}
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4 add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1 create_partition -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 0 -min_pitch_right 0 -min_pitch_top 2 -min_pitch_bottom 0 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 0 0 0 -route_halo 0.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4 add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
\ No newline at end of file
ASIC/44pin/Cadence/scripts/pnr_flow.tcl
View file @ 2dc8b4aa
###################################### #-----------------------------------------------------------------------------
# Script : Place and Route Flow # NanoSoC Place and route script for Cadence Innovus
# Date : 25th May 2023 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
# Author : Srimanth Tenneti #
# Description : Innovus PnR Flow # run: innovus -stylus -f pnr_flow.tcl
###################################### # Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
puts "Starting PnR Flow ..." puts "Starting PnR Flow ..."
...@@ -26,16 +38,18 @@ source power_plan.tcl ...@@ -26,16 +38,18 @@ source power_plan.tcl
source power_route.tcl source power_route.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
uniquify nanosoc_chip_pads -verbose
### Placement ### Placement
source place.tcl source place.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware false
uniquify nanosoc_chip_pads -verbose
### CTS ### CTS
source clock_tree_synthesis.tcl source clock_tree_synthesis.tcl
reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware true
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
...@@ -71,6 +85,10 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_ ...@@ -71,6 +85,10 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_
gui_show gui_show
write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
-map_file $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/tech.map \
-lib_name DesignLib \
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 2000 -mode all
ASIC/44pin/Cadence/scripts/power_plan.tcl
View file @ 2dc8b4aa
...@@ -10,7 +10,7 @@ connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name * ...@@ -10,7 +10,7 @@ connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name * connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name * connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name * connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -override connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -override
### Top and Bottom Metal Declartions ### Top and Bottom Metal Declartions
set_db add_rings_stacked_via_top_layer M8 set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1 set_db add_rings_stacked_via_bottom_layer M1
...@@ -38,12 +38,12 @@ set_db add_stripes_orthogonal_only true ...@@ -38,12 +38,12 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring } set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell } set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape } set_db add_stripes_skip_via_on_wire_shape { noshape }
add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 50 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 58 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all deselect_obj -all
# Connect Accelerator region # Connect Accelerator region
select_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator select_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator
set_db add_stripes_ignore_block_check true set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false set_db add_stripes_route_over_rows_only false
...@@ -69,7 +69,7 @@ add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing ...@@ -69,7 +69,7 @@ add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing
deselect_obj -all deselect_obj -all
# connect Macros # connect Macros
select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] select_obj [ list u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
set_db add_stripes_ignore_block_check false set_db add_stripes_ignore_block_check false
set_db add_stripes_break_at none set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false set_db add_stripes_route_over_rows_only false
......
ASIC/constraints.sdc
View file @ 2dc8b4aa
...@@ -16,15 +16,15 @@ set SWDCLK "swdclk"; ...@@ -16,15 +16,15 @@ set SWDCLK "swdclk";
set_units -time ns; set_units -time ns;
set_units -capacitance pF; set_units -capacitance pF;
set EXTCLK_PERIOD 4; set EXTCLK_PERIOD 4.1666;
set SWDCLK_PERIOD 20; set SWDCLK_PERIOD 16.66666;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK] create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK] create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.800 set SKEW 0.800
set_clock_uncertainty [expr 0.15*$EXTCLK_PERIOD] [get_clocks $EXTCLK] set_clock_uncertainty [expr 0.17*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
set_clock_uncertainty [expr 0.15*$SWDCLK_PERIOD] [get_clocks $SWDCLK] set_clock_uncertainty [expr 0.17*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
set MINRISE 0.20 set MINRISE 0.20
set MAXRISE 0.25 set MAXRISE 0.25
...@@ -43,9 +43,12 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK] ...@@ -43,9 +43,12 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
### Multicycle path through pads ### Multicycle path through pads
set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/* #set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/* set_false_path -through uPAD_SWDIO_IO
set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/* set_false_path -through uPAD_P0_*
set_false_path -through uPAD_P1_*
#set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
#set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
#### DELAY DEFINITION #### DELAY DEFINITION
......
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
View file @ 2dc8b4aa
...@@ -35,6 +35,8 @@ ...@@ -35,6 +35,8 @@
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller // Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// //
`include "gen_defines.v"
module nanosoc_chip_pads ( module nanosoc_chip_pads (
inout wire VDDIO, inout wire VDDIO,
inout wire VSSIO, inout wire VSSIO,
...@@ -189,9 +191,9 @@ nanosoc_chip_cfg #( ...@@ -189,9 +191,9 @@ nanosoc_chip_cfg #(
.bist_enable (soc_bist_enable ), .bist_enable (soc_bist_enable ),
.bist_in (soc_bist_in ), // soc bist control inputs .bist_in (soc_bist_in ), // soc bist control inputs
.bist_out (soc_bist_out ), // soc test status outputs .bist_out (soc_bist_out ), // soc test status outputs
.alt_mode (soc_alt_mode )// ALT MODE = UART .alt_mode (soc_alt_mode ),// ALT MODE = UART
.uart_rxd_i (soc_uart_rxd_i ) // UART RXD .uart_rxd_i (soc_uart_rxd_i ), // UART RXD
.uart_txd_o (soc_uart_txd_o ) // UART TXD .uart_txd_o (soc_uart_txd_o ), // UART TXD
.swd_mode (soc_swd_mode ), // SWD mode .swd_mode (soc_swd_mode ), // SWD mode
`endif `endif
.clk_i(pad_clk_i), .clk_i(pad_clk_i),
......
makefile
View file @ 2dc8b4aa
...@@ -77,7 +77,7 @@ else ...@@ -77,7 +77,7 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
NANOSOC_DEFINES += DMAC_DMA350 POWER_PINS NANOSOC_DEFINES += DMAC_0_PL230 DMAC_1_PL230 ASIC_TEST_PORTS POWER_PINS
else else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
......
software/common/validation/apb_mux_tests.c
View file @ 2dc8b4aa
...@@ -125,9 +125,9 @@ int main (void) ...@@ -125,9 +125,9 @@ int main (void)
puts ("11: APB test slave"); puts ("11: APB test slave");
if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11; if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11;
//puts ("12: DMAC 1 (Not Implemented) - Slave Error"); //puts ("12: DMAC 1 (Not Implemented) - Slave Error");
// if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12; // if ( ID_Check(&pl230_udma_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12;
puts ("13: blank - default slave (generates slave error)"); //puts ("13: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13; // if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13;
puts ("14: Debug USRT"); puts ("14: Debug USRT");
if ( ID_Check(&apb_uart_id[0], CMSDK_USRT2_BASE ) == 1 ) err_code |= 1<<14; if ( ID_Check(&apb_uart_id[0], CMSDK_USRT2_BASE ) == 1 ) err_code |= 1<<14;
//puts ("15: DMAC 0 (PL230)"); //puts ("15: DMAC 0 (PL230)");
......
testcodes/apb_mux_tests/apb_mux_tests.hex
View file @ 2dc8b4aa
...@@ -2,12 +2,12 @@ ...@@ -2,12 +2,12 @@
04 04
00 00
30 30
0D BD
0A 09
00 00
00 00
15 C5
0A 09
00 00
00 00
87 87
...@@ -42,8 +42,8 @@ ...@@ -42,8 +42,8 @@
00 00
00 00
00 00
19 C9
0A 09
00 00
00 00
00 00
...@@ -54,140 +54,140 @@ ...@@ -54,140 +54,140 @@
00 00
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1B CB
0A 09
00 00
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1D CD
0A 09
00 00
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1F CF
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1F CF
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1F CF
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00 00
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1F CF
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00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
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00 00
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1F CF
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00 00
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1F CF
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00 00
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1F CF
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00 00
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1F CF
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00 00
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1F CF
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00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
1F CF
0A 09
00 00
00 00
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...@@ -250,12 +250,12 @@ AB ...@@ -250,12 +250,12 @@ AB
43 43
18 18
47 47
B0 E8
0C 0C
00 00
00 00
D0 08
0C 0D
00 00
00 00
10 10
...@@ -322,7 +322,7 @@ B5 ...@@ -322,7 +322,7 @@ B5
D1 D1
00 00
F0 F0
01 1D
FD FD
10 10
BD BD
...@@ -340,7 +340,7 @@ B5 ...@@ -340,7 +340,7 @@ B5
BD BD
00 00
F0 F0
C2 DE
FD FD
11 11
46 46
...@@ -354,7 +354,7 @@ F0 ...@@ -354,7 +354,7 @@ F0
F9 F9
00 00
F0 F0
DA F6
FD FD
03 03
B4 B4
...@@ -366,7 +366,7 @@ FF ...@@ -366,7 +366,7 @@ FF
BC BC
00 00
F0 F0
7C 54
FC FC
00 00
00 00
...@@ -414,7 +414,7 @@ F3 ...@@ -414,7 +414,7 @@ F3
47 47
00 00
00 00
E3 D1
08 08
00 00
00 00
...@@ -424,7 +424,7 @@ B5 ...@@ -424,7 +424,7 @@ B5
20 20
87 87
B0 B0
CC CD
4D 4D
05 05
90 90
...@@ -462,12 +462,12 @@ AE ...@@ -462,12 +462,12 @@ AE
DD DD
6E 6E
60 60
C3 C4
A0 A0
00 00
F0 F0
E5 01
FC FD
03 03
20 20
09 09
...@@ -522,11 +522,11 @@ BE ...@@ -522,11 +522,11 @@ BE
42 42
05 05
D0 D0
BF C0
A0 A0
00 00
F0 F0
57 73
FC FC
05 05
98 98
...@@ -550,11 +550,11 @@ D0 ...@@ -550,11 +550,11 @@ D0
28 28
0F 0F
DD DD
C4 C5
A0 A0
00 00
F0 F0
B9 D5
FC FC
01 01
20 20
...@@ -570,11 +570,11 @@ FF ...@@ -570,11 +570,11 @@ FF
20 20
E1 E1
E7 E7
CA CB
A0 A0
00 00
F0 F0
AF CB
FC FC
02 02
20 20
...@@ -582,11 +582,11 @@ FC ...@@ -582,11 +582,11 @@ FC
B0 B0
F0 F0
BD BD
D3 D4
A0 A0
00 00
F0 F0
A9 C5
FC FC
00 00
20 20
...@@ -626,7 +626,7 @@ D0 ...@@ -626,7 +626,7 @@ D0
D0 D0
6D 6D
1C 1C
D3 D4
49 49
21 21
60 60
...@@ -638,7 +638,7 @@ D3 ...@@ -638,7 +638,7 @@ D3
D0 D0
6D 6D
1C 1C
D1 D2
49 49
21 21
80 80
...@@ -650,7 +650,7 @@ D1 ...@@ -650,7 +650,7 @@ D1
D0 D0
6D 6D
1C 1C
CF D0
49 49
61 61
80 80
...@@ -710,7 +710,7 @@ E1 ...@@ -710,7 +710,7 @@ E1
D0 D0
6D 6D
1C 1C
C1 C2
49 49
A1 A1
80 80
...@@ -764,7 +764,7 @@ C3 ...@@ -764,7 +764,7 @@ C3
D0 D0
6D 6D
1C 1C
B5 B6
49 49
E1 E1
81 81
...@@ -778,13 +778,13 @@ D0 ...@@ -778,13 +778,13 @@ D0
1C 1C
00 00
27 27
73 74
49 49
00 00
20 20
C8 C8
60 60
72 73
4A 4A
01 01
21 21
...@@ -808,7 +808,7 @@ FF ...@@ -808,7 +808,7 @@ FF
F7 F7
25 25
FF FF
6C 6D
48 48
40 40
68 68
...@@ -818,7 +818,7 @@ FF ...@@ -818,7 +818,7 @@ FF
D1 D1
76 76
1C 1C
69 6A
49 49
00 00
20 20
...@@ -830,7 +830,7 @@ FF ...@@ -830,7 +830,7 @@ FF
F7 F7
1E 1E
FF FF
66 67
49 49
C8 C8
60 60
...@@ -850,7 +850,7 @@ D1 ...@@ -850,7 +850,7 @@ D1
2F 2F
DB DB
DB DB
61 62
49 49
00 00
20 20
...@@ -862,11 +862,11 @@ DB ...@@ -862,11 +862,11 @@ DB
2D 2D
04 04
DD DD
9D 9E
A0 A0
00 00
F0 F0
1D 39
FC FC
01 01
20 20
...@@ -876,21 +876,21 @@ BD ...@@ -876,21 +876,21 @@ BD
2E 2E
04 04
DD DD
A3 A4
A0 A0
00 00
F0 F0
16 32
FC FC
01 01
20 20
F8 F8
BD BD
A9 AA
A0 A0
00 00
F0 F0
11 2D
FC FC
00 00
20 20
...@@ -902,27 +902,27 @@ B5 ...@@ -902,27 +902,27 @@ B5
24 24
00 00
F0 F0
71 49
FB FB
AD AE
A0 A0
00 00
F0 F0
08 24
FC FC
B6 B7
A0 A0
00 00
F0 F0
05 21
FC FC
C3 C4
A0 A0
00 00
F0 F0
02 1E
FC FC
4F 50
49 49
00 00
20 20
...@@ -932,17 +932,17 @@ C8 ...@@ -932,17 +932,17 @@ C8
60 60
88 88
60 60
CD CE
A0 A0
00 00
F0 F0
FA 16
FB FC
01 01
21 21
89 89
07 07
CD CE
48 48
FF FF
F7 F7
...@@ -954,15 +954,15 @@ FE ...@@ -954,15 +954,15 @@ FE
D1 D1
01 01
24 24
CB CC
A0 A0
00 00
F0 F0
EF 0B
FB FC
CD CE
49 49
C8 C9
48 48
FF FF
F7 F7
...@@ -976,15 +976,15 @@ D1 ...@@ -976,15 +976,15 @@ D1
20 20
04 04
43 43
CA CB
A0 A0
00 00
F0 F0
E4 00
FB FC
CC
49
CD CD
49
CE
48 48
FF FF
F7 F7
...@@ -998,15 +998,15 @@ D1 ...@@ -998,15 +998,15 @@ D1
20 20
04 04
43 43
CA CB
A0 A0
00 00
F0 F0
D9 F5
FB FB
D6 D7
49 49
D6 D7
48 48
FF FF
F7 F7
...@@ -1020,15 +1020,15 @@ D1 ...@@ -1020,15 +1020,15 @@ D1
20 20
04 04
43 43
D4 D5
A0 A0
00 00
F0 F0
CE EA
FB FB
D9 DA
49 49
D1 D2
48 48
FF FF
F7 F7
...@@ -1042,15 +1042,15 @@ D1 ...@@ -1042,15 +1042,15 @@ D1
20 20
04 04
43 43
D6 D7
A0 A0
00 00
F0 F0
C3 DF
FB FB
DC DD
49 49
CB CC
48 48
FF FF
F7 F7
...@@ -1064,15 +1064,15 @@ D1 ...@@ -1064,15 +1064,15 @@ D1
20 20
04 04
43 43
D9 DA
A0 A0
00 00
F0 F0
B8 D4
FB FB
DA
49
DB DB
49
DC
48 48
FF FF
F7 F7
...@@ -1086,15 +1086,15 @@ D1 ...@@ -1086,15 +1086,15 @@ D1
20 20
04 04
43 43
D8 D9
A0 A0
00 00
F0 F0
AD C9
FB FB
E4 E5
49 49
C0 C1
48 48
FF FF
F7 F7
...@@ -1108,15 +1108,15 @@ D1 ...@@ -1108,15 +1108,15 @@ D1
20 20
04 04
43 43
E1 E2
A0 A0
00 00
F0 F0
A2 BE
FB FB
E2
49
E3 E3
49
E4
48 48
FF FF
F7 F7
...@@ -1130,15 +1130,15 @@ D1 ...@@ -1130,15 +1130,15 @@ D1
02 02
04 04
43 43
E0 E1
A0 A0
00 00
F0 F0
97 B3
FB FB
EC ED
49 49
B5 B6
48 48
FF FF
F7 F7
...@@ -1152,15 +1152,15 @@ D1 ...@@ -1152,15 +1152,15 @@ D1
02 02
04 04
43 43
E9 EA
A0 A0
00 00
F0 F0
8C A8
FB FB
F4 F5
49 49
B0 B1
48 48
FF FF
F7 F7
...@@ -1174,13 +1174,13 @@ D1 ...@@ -1174,13 +1174,13 @@ D1
02 02
04 04
43 43
F1 F2
A0 A0
00 00
F0 F0
81 9D
FB FB
F5 F6
48 48
FF FF
F7 F7
...@@ -1194,15 +1194,15 @@ C0 ...@@ -1194,15 +1194,15 @@ C0
02 02
04 04
43 43
F2 F3
A0 A0
00 00
F0 F0
77 93
FB FB
FE F6
49 49
A5 BB
48 48
FF FF
F7 F7
...@@ -1212,34 +1212,38 @@ FE ...@@ -1212,34 +1212,38 @@ FE
28 28
01 01
D1 D1
40 80
03 03
04 04
43 43
00
2C
07
D0
21
46
F1
A0
00
F0
15
FB FB
00
F0
F2
FA
00
20
10
BD
F9
A0 A0
00 00
F0 F0
6C 0E
FB FB
FD
49
B5
48
FF
F7 F7
6A E7
FE
01
28
01
D1
80
03
F5
E1
F5
E1
00 00
00 00
00 00
...@@ -1766,7 +1770,7 @@ C5 ...@@ -1766,7 +1770,7 @@ C5
30 30
00 00
00 00
44 7C
0D 0D
00 00
00 00
...@@ -1806,7 +1810,7 @@ C5 ...@@ -1806,7 +1810,7 @@ C5
20 20
00 00
40 40
54 8C
0D 0D
00 00
00 00
...@@ -1866,7 +1870,7 @@ C5 ...@@ -1866,7 +1870,7 @@ C5
30 30
00 00
40 40
74 AC
0D 0D
00 00
00 00
...@@ -1950,7 +1954,7 @@ C5 ...@@ -1950,7 +1954,7 @@ C5
60 60
00 00
40 40
34 6C
0D 0D
00 00
00 00
...@@ -2026,7 +2030,7 @@ C5 ...@@ -2026,7 +2030,7 @@ C5
80 80
00 00
40 40
64 9C
0D 0D
00 00
00 00
...@@ -2167,62 +2171,6 @@ B0 ...@@ -2167,62 +2171,6 @@ B0
00 00
40 40
31 31
33
3A
20
62
6C
61
6E
6B
20
2D
20
64
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66
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75
6C
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73
6C
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76
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28
67
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6E
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72
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74
65
73
20
73
6C
61
76
65
20
65
72
72
6F
72
29
00
00
00
00
D0
00
40
31
34 34
3A 3A
20 20
...@@ -2242,39 +2190,73 @@ D0 ...@@ -2242,39 +2190,73 @@ D0
E0 E0
00 00
40 40
04 0A
43 2A
00 2A
2C 20
07 54
D0 45
21 53
54
20
46 46
18 41
A0 49
4C
45
44
20
2A
2A
2C
20
45
72
72
6F
72
20
63
6F
64
65
20
3D
20
28
30
78
25
78
29
0A
00
00 00
F0
F7
F8
00 00
F0
E6
F8
00 00
0A
2A
2A
20 20
10 54
BD 45
53
54
20 20
A0 50
41
53
53
45
44
20
2A
2A
0A
00 00
F0
F0
F8
F7
E7
70 70
B5 B5
22 13
4C 4C
05 05
46 46
...@@ -2290,11 +2272,11 @@ B5 ...@@ -2290,11 +2272,11 @@ B5
28 28
02 02
D0 D0
1F 10
A0 A0
00 00
F0 F0
53 78
F9 F9
A0 A0
68 68
...@@ -2312,107 +2294,45 @@ AE ...@@ -2312,107 +2294,45 @@ AE
28 28
09 09
D0 D0
20 10
A0
00
F0
D8
F8
20
68
00
28
03
D0
31
46
22
A0
00
F0
D1
F8
27
48
28
60
70
BD
26
A0 A0
00 00
F0 F0
3B FD
F9
00
F0
BA
F8 F8
FE
E7
0A
2A
2A
20
54
45
53
54
20
46
41
49
4C
45
44
20
2A
2A
2C
20
45
72
72
6F
72
20
63
6F
64
65
20
3D
20 20
28 68
30
78
25
78
29
0A
00 00
28
03
D0
31
46
13
A0
00 00
F0
F6
F8
17
48
28
60
70
BD
17
A0
00 00
F0
60
F9
00
F0
CD
F8
FE
E7
00 00
0A
2A
2A
20
54
45
53
54
20
50
41
53
53
45
44
20
2A
2A
0A
00 00
00 00
00 00
...@@ -2563,9 +2483,9 @@ E7 ...@@ -2563,9 +2483,9 @@ E7
70 70
47 47
00 00
E1 1C
F5 4E
05 0E
10 10
00 00
00 00
...@@ -2602,7 +2522,7 @@ E7 ...@@ -2602,7 +2522,7 @@ E7
47 47
00 00
00 00
FD AD
09 09
00 00
00 00
...@@ -2632,7 +2552,7 @@ C0 ...@@ -2632,7 +2552,7 @@ C0
B2 B2
00 00
F0 F0
1E 36
F8 F8
10 10
BD BD
...@@ -2640,11 +2560,11 @@ BD ...@@ -2640,11 +2560,11 @@ BD
B5 B5
00 00
F0 F0
20 42
F8 F8
00 00
F0 F0
18 30
F8 F8
10 10
BD BD
...@@ -2660,42 +2580,96 @@ C0 ...@@ -2660,42 +2580,96 @@ C0
B2 B2
00 00
F0 F0
10 28
F8 F8
10 10
BD BD
FE FE
E7 E7
41 2E
20 48
10 00
21
81
60
2E
49 49
40
01 01
08
61 61
01 01
22 21
8A 81
60 60
0E 2D
49 48
08
61
03 03
21
01
61
81
60
2C
49
20
20 20
88 88
61
70
47
2C
48
2A
49
01
60 60
0D 2B
49
81
61
01
21
C1
60
C3
21
81
60
01
69
C9
07
FC
D0
24
49 49
20 20
20 20
88 88
61 61
21
48
00
21
81
60
30
21
01
61
03
21
81
60
70 70
47 47
0A 1D
49 49
8A
68
D2
07
04
D0
4A 4A
68 68
D2 D2
...@@ -2706,13 +2680,59 @@ D1 ...@@ -2706,13 +2680,59 @@ D1
60 60
70 70
47 47
17
4A
53
68
DB
07 07
FC
D1
10
60
08
60
70
47
13
4B
15
48 48
59
68
42
68
89
07
C9
17
92
07
D2
17
49
1C
52
1C
11
42
F5
D1
59
68
89
07
01
D5
18
68
03
E0
41 41
68 68
89 89
07 07
FC 01
D5 D5
00 00
68 68
...@@ -2720,24 +2740,48 @@ C0 ...@@ -2720,24 +2740,48 @@ C0
B2 B2
70 70
47 47
04 0A
48 48
04 04
22 21
41 82
68 68
C9 D2
07
04
D0
42
68
D2
07 07
FC FC
D1 D1
02 01
60 60
FE FE
E7 E7
03
4A
53
68
DB
07
FC
D1
11
60
01
60
F7
E7
00 00
60 60
00 00
40 40
6A
18
00
00
00 00
E0 E0
00 00
...@@ -2746,6 +2790,18 @@ E0 ...@@ -2746,6 +2790,18 @@ E0
10 10
01 01
40 40
8E
0C
01
00
00
20
00
40
24
F4
00
00
70 70
47 47
00 00
...@@ -2844,8 +2900,8 @@ FF ...@@ -2844,8 +2900,8 @@ FF
46 46
FF FF
F7 F7
0E F2
FB FA
00 00
28 28
08 08
...@@ -2982,7 +3038,7 @@ B5 ...@@ -2982,7 +3038,7 @@ B5
E0 E0
FF FF
F7 F7
4D 09
FF FF
40 40
1C 1C
...@@ -3002,8 +3058,8 @@ D1 ...@@ -3002,8 +3058,8 @@ D1
20 20
FF FF
F7 F7
43
FF FF
FE
10 10
BD BD
00 00
...@@ -3220,7 +3276,7 @@ F8 ...@@ -3220,7 +3276,7 @@ F8
46 46
FF FF
F7 F7
E1 9D
FE FE
00 00
28 28
...@@ -3238,7 +3294,7 @@ BD ...@@ -3238,7 +3294,7 @@ BD
BD BD
00 00
00 00
B7 2F
FD FD
FF FF
FF FF
...@@ -3316,7 +3372,7 @@ B0 ...@@ -3316,7 +3372,7 @@ B0
B5 B5
FF FF
F7 F7
94 50
FE FE
60 60
BC BC
...@@ -3364,7 +3420,7 @@ C0 ...@@ -3364,7 +3420,7 @@ C0
46 46
FF FF
F7 F7
1F 03
FA FA
10 10
BD BD
...@@ -3498,8 +3554,8 @@ B1 ...@@ -3498,8 +3554,8 @@ B1
30 30
78 78
00 00
CC 04
0D 0E
00 00
00 00
00 00
...@@ -3514,8 +3570,8 @@ CC ...@@ -3514,8 +3570,8 @@ CC
01 01
00 00
00 00
E4 1C
0D 0E
00 00
00 00
18 18
...@@ -3547,9 +3603,9 @@ E4 ...@@ -3547,9 +3603,9 @@ E4
00 00
00 00
00 00
E1 1C
F5 4E
05 0E
00 00
00 00
00 00
......