verif/tb/verilog/nanosoc_tb_qs.v

@@ -39,8 +39,8 @@
 
 module nanosoc_tb_qs;
 
-  wire        XTAL1;   // crystal pin 1
-  wire        XTAL2;   // crystal pin 2
+  wire        CLK;   // crystal pin 1
+  wire        TEST = 1'b0;   // crystal pin 2
   wire        NRST;    // active low reset
 
   wire [15:0] P0;      // Port 0
@@ -93,7 +93,7 @@ SROM_Ax32
     .romgen (1)
    )
    u_BOOTROM (
-    .CLK(XTAL1),
+    .CLK(CLK),
     .ADDR(8'h0),
     .SEL(1'b0),
     .RDATA( )
@@ -111,13 +111,13 @@ SROM_Ax32
   .VDD        (VDD),
   .VSS        (VSS),
 `endif
-  .XTAL1      (XTAL1),  // input
-  .XTAL2      (XTAL2),  // output
+  .CLK        (CLK),  // input
+  .TEST       (TEST),  // output
   .NRST       (NRST),   // active low reset
   .P0         (P0),
   .P1         (P1),
-  .SWDIOTMS   (SWDIOTMS),
-  .SWCLKTCK   (SWCLKTCK)
+  .SWDIO      (SWDIOTMS),
+  .SWDCK      (SWCLKTCK)
   );
 
  // --------------------------------------------------------------------------------
@@ -125,7 +125,7 @@ SROM_Ax32
  // --------------------------------------------------------------------------------
  `ifndef COCOTB_SIM
   nanosoc_clkreset u_nanosoc_clkreset(
-  .CLK  (XTAL1),
+  .CLK  (CLK),
   .NRST (NRST)
   );
   `endif
@@ -172,7 +172,7 @@ SROM_Ax32
   // If PCLK is running at slower speed, the UART output will also be slower
   assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
 `else
-  assign PCLK = XTAL1;
+  assign PCLK = CLK;
 `endif
 
  // --------------------------------------------------------------------------------
@@ -273,7 +273,7 @@ reg baud_clk_del;
   nanosoc_axi_stream_io_8_txd_from_file #(
     .TXDFILENAME(ADP_FILENAME)
   ) u_nanosoc_axi_stream_io_8_txd_from_file (
-    .aclk       (XTAL1),
+    .aclk       (CLK),
     .aresetn    (NRST),
     .txd8_ready (txd8_tready),
     .txd8_valid (txd8_tvalid),
@@ -294,7 +294,7 @@ reg baud_clk_del;
   .ft_miosio_i  (ft_miosio_i),
   .ft_miosio_o  (ft_miosio_o),
   .ft_miosio_z  (ft_miosio_z),
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .rxd_tready_o (txd8_tready),
   .rxd_tvalid_i (txd8_tvalid),
@@ -308,7 +308,7 @@ reg baud_clk_del;
   nanosoc_axi_stream_io_8_rxd_to_file#(
     .RXDFILENAME("logs/ft1248_out.log")
   ) u_nanosoc_axi_stream_io_8_rxd_to_file (
-    .aclk         (XTAL1),
+    .aclk         (CLK),
     .aresetn      (NRST),
     .rxd8_ready   (rxd8_tready),
     .rxd8_valid   (rxd8_tvalid),
@@ -319,7 +319,7 @@ reg baud_clk_del;
 nanosoc_track_tb_iostream
   u_nanosoc_track_tb_iostream
   (
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .rxd8_ready   (rxd8_tready),
   .rxd8_valid   (rxd8_tvalid),
@@ -340,7 +340,7 @@ nanosoc_ft1248x1_track
   .ft_ssn_i     (ft_ssn_out),
   .ft_miso_i    (ft_miso_in),
   .ft_miosio_i  (ft_miosio_i),
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .FTDI_CLK2UART_o      (ft_clk2uart),  // Clock (baud rate)
   .FTDI_OP2UART_o       (ft_rxd2uart),  // Received data to UART capture
@@ -582,7 +582,7 @@ nanosoc_ft1248x1_track
   u_cmsdk_debug_tester
   (
    // Clock and Reset
-   .CLK                                 (XTAL1),
+   .CLK                                 (CLK),
    .PORESETn                            (NRST),
 
    // Command Interface