flist/nanosoc_vip.flist

@@ -28,3 +28,4 @@ $(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_datafile.v

flows/makefile.software

@@ -73,6 +73,9 @@ endif
 	    mkdir -p $(SIM_DIR) ; \
 	    cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
 	    cp adp.cmd $(SIM_DIR)/adp.cmd ; \
+	    if [ -e data_in.csv ] ; then \
+	  	cp data_in.csv $(SIM_DIR)/data_in.csv ; \
+	    fi ;\
 	  else \
 	    while [ ! -e $(TESTNAME).hex ] ; do \
 	      echo Wait for $(TESTNAME).hex file ...; \
@@ -94,6 +97,9 @@ endif
 	  if [ -e expram_h.hex ] ; then \
 	  	cp expram_h.hex $(SIM_DIR)/expram_h.hex ; \
 	  fi ;\
+	  if [ -e data_in.csv ] ; then \
+	  	cp data_in.csv $(SIM_DIR)/data_in.csv ; \
+	  fi ;\
 	  cd $(SIM_DIR) ;\
 	elif [ -d "$(PROJ_SW_DIR)/$(TESTNAME)" ] ; then \
 	  cd $(PROJ_SW_DIR)/$(TESTNAME) ;\
@@ -105,6 +111,9 @@ endif
 	    mkdir -p $(SIM_DIR) ; \
 	    cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
 	    cp adp.cmd $(SIM_DIR)/adp.cmd ; \
+	    if [ -e data_in.csv ] ; then \
+	  	cp data_in.csv $(SIM_DIR)/data_in.csv ; \
+	    fi ;\
 	  else \
 	    while [ ! -e $(TESTNAME).hex ] ; do \
 	      echo Wait for $(TESTNAME).hex file ...; \
@@ -202,4 +211,4 @@ clean_all_code:
 # Remove only bootloader and default selected test
 clean_code:
 	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; $(MAKE) clean; cd $(SIM_DIR); )
-	@(cd $(TESTCODES_DIR)/$(TESTNAME)   ; $(MAKE) clean; cd $(SIM_DIR); )
\ No newline at end of file
+	@(cd $(TESTCODES_DIR)/$(TESTNAME)   ; $(MAKE) clean; cd $(SIM_DIR); )

socdebug_tech @ 9ef8d848

-Subproject commit 049294a8aa4385e4b2e2a03210b315a574e2a787
+Subproject commit 9ef8d848da72e57f806b24eed5c2f6bbdce66668

testcodes/dataio_tests/data_in.csv

+0000100101000110,0000110001000110,0000110001000110,0000100101000110,0000011001000110,0000011001000110,0000010101000110,0000100001000110,0000110101000110,0000101101000110,0000100001000110,0000010001000110,0000001101000110,0000100001000110,0000100101000110,0000101001000110,0000100101000111,0000010101000111,0000010101000111,0000010101000111,0000011101000111,0000100101000111,0000101001000111,0000100001000111,0000010001000111,0000001001000111,0000010001000111,0000100001000111,0000101101000111,0000100101000111,0000011001000111,0000010001000111,0000010001000111,0000011001000111,0000100101000111,0000101001000111,0000100101000111,0000010101000111,0000001001000111,0000010101000111
+0000010100101010,1111110100101010,0000010100101010,0000000100101001,1111111000101010,0000011000101001,0000000100101001,0000010100101000,0000010100101000,0000000100101000,0000101100101000,0000101000101000,0000011100100111,0000101000101000,0000101100100111,0000110100100111,0000101100100111,0000100100100111,0000111000100111,0000101000100111,0000001100100111,0000101000100111,0000011100100110,0000001000100110,0000011100100110,0000011100100110,0000100100100110,0000101000100110,0000001100100101,0000101000100101,0000010100100101,0000000000100101,0000011000100101,0000010000100101,0000001000100100,0000010000100100,1111111100100101,0000011000100100,0000001000100100,1111110000100100
+0000000000000000,0000000000000001,0000000000000011,0000000000000111,0000000000001111,0000000000011111,0000000000111111,0000000001111111,0000000011111111,0000000111111111,0000001111111111,0000011111111111,0000111111111111,0001111111111111,0011111111111111,0111111111111111,1111111111111111
+1111111111111111,1111111111111110,1111111111111100,1111111111111000,1111111111110000,1111111111100000,1111111111000000,1111111110000000,1111111100000000,1111111000000000,1111110000000000,1111100000000000,1111000000000000,1110000000000000,1100000000000000,1000000000000000,0000000000000000
+0000000000000000,0000000000000001,0000000000000010,0000000000000100,0000000000001000,0000000000010000,0000000000100000,0000000001000000,0000000010000000,0000000100000000,0000001000000000,0000010000000000,0000100000000000,0001000000000000,0010000000000000,0100000000000000,1000000000000000
+

testcodes/dataio_tests/dataio_functions.c

+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2025 SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+#include "CMSDK_CM0.h"
+
+#define DATA_UART  ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE   )
+
+#define UART_STATE_TXFULL CMSDK_UART_STATE_TXBF_Msk
+#define UART_STATE_RXFULL CMSDK_UART_STATE_RXBF_Msk
+
+#define UART_CTRL_TXEN         CMSDK_UART_CTRL_TXEN_Msk
+#define UART_CTRL_RXEN         CMSDK_UART_CTRL_RXEN_Msk
+#define UART_CTRL_TXRXEN       (CMSDK_UART_CTRL_TXEN_Msk + CMSDK_UART_CTRL_RXEN_Msk)
+#define UART_CTRL_TXIRQEN      (CMSDK_UART_CTRL_TXIRQEN_Msk + UART_CTRL_TXRXEN)
+#define UART_CTRL_RXIRQEN      (CMSDK_UART_CTRL_RXIRQEN_Msk + UART_CTRL_TXRXEN)
+
+
+unsigned int DataIO_enable(void) {
+  DATA_UART->CTRL    = 0x00;             // re-initialise/flush
+  DATA_UART->CTRL    = UART_CTRL_TXRXEN; // enble TX and RX
+  return(0);
+}
+
+unsigned int DataIO_init(void) {
+  DATA_UART->CTRL    = 0x00;             // re-initialise/flush
+  DATA_UART->CTRL    = UART_CTRL_TXRXEN; // enble TX and RX
+  return(0);
+}
+
+// Output ready check
+unsigned int DataIO_putc_ready(void) {
+  return((DATA_UART->STATE & UART_STATE_TXFULL) == 0); // ready if TXBUF empty
+}
+
+// Output Busy check
+unsigned int DataIO_putc_busy(void) {
+  return((DATA_UART->STATE & UART_STATE_TXFULL) != 0); // busy if TXBUF full
+}
+
+// Output a character
+unsigned char DataIO_putc(unsigned char my_ch) {
+  while (DataIO_putc_busy()) ; // busy wait
+  DATA_UART->DATA = my_ch; // output the character
+  return (my_ch);
+}
+
+
+// Output a (zero-terminated) string
+void DataIO_puts(unsigned char * mytext) {
+  unsigned char string_ch;
+  do {
+    string_ch = *mytext;
+    if (string_ch != (char) 0x0) {
+      DataIO_putc(string_ch);  // Normal data
+      }
+    *mytext++;
+  } while (string_ch != 0);
+  return;
+}
+
+// Input ready check
+unsigned int DataIO_getc_ready(void) {
+  return((DATA_UART->STATE & UART_STATE_RXFULL) != 0); // ready if RXBUF set
+}
+
+
+// Input Busy check
+unsigned int DataIO_getc_busy(void) {
+  return((DATA_UART->STATE & UART_STATE_RXFULL) == 0); // busy if RXBUF not set
+}
+
+// Input a character
+unsigned char DataIO_getc(void) {
+  while (DataIO_getc_busy()) ; // busy wait
+  return (DATA_UART->DATA);
+}

testcodes/dataio_tests/dataio_functions.h

+//-----------------------------------------------------------------------------
+// customised Cortex-M0 'nanosoc' controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2025 SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+// IO enable
+extern unsigned int DataIO_enable(void);
+extern unsigned int DataIO_init(void);
+
+// Output ready check
+extern unsigned char DataIO_putc_ready(void);
+
+// Output busy check
+extern unsigned int DataIO_putc_busy(void);
+
+// Output a character
+extern unsigned char DataIO_putc(unsigned char my_ch);
+
+// DataIO string output
+extern void DataIO_puts(unsigned char * mytext);
+
+// Input ready check
+extern unsigned int DataIO_getc_ready(void);
+
+// Input busy check
+extern unsigned int DataIO_getc_busy(void);
+
+// Input a character
+extern unsigned char DataIO_getc(void);
+
+/* example usage
+
+#include "CMSDK_CM0.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+
+#include "DataIO_functions.h"
+
+int main(void) {
+  unsigned char ch;
+  char tx_buf[32];
+  
+  
+  UartStdOutInit(); // console channel init
+  printf("Data Channel CSV Reader/Writer (ASC binary -> Hex) tests\n");
+  DataIO_init();  // datachannel init
+    do { // rx process CSV entry
+      if (DataIO_getc_ready()) {
+        ch = DataIO_Getc();
+        // ...
+      }
+    
+    DataIO_puts((unsigned char*) tx_buf);
+    
+    do { // tx process
+      if (DataIO_putc_ready()) {
+        DataIO_putc(tx_buf[<i>]);
+      }
+
+*/
+
+

testcodes/dataio_tests/dataio_tests.c

+#include "CMSDK_CM0.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+
+#include "dataio_functions.h"
+
+
+int main(void) {
+  unsigned char ch;
+  char         tx_buf[20];
+  unsigned int tx_count;
+  unsigned int rx_count;
+  unsigned int value;
+  unsigned int end_of_record ;
+  unsigned int end_of_data ;
+////  FILE *datain, *dataout;
+  
+  UartStdOutInit();
+  printf("Data Channel CSV Reader/Writer (ASC binary -> Hex) tests\n");
+
+  DataIO_init();
+
+  end_of_data = 0;
+  do { // record at a time 
+    tx_count = 0;
+    rx_count = 0;
+    value    = 0;
+    end_of_record = 0;
+    do { // rx process CSV entry
+      if (DataIO_getc_ready()) {
+        ch = DataIO_getc();
+        if  (ch == '0') { value = (value << 1);      rx_count++; }
+        if  (ch == '1') { value = (value << 1) + 1;  rx_count++; }
+        if  (ch == ',')  end_of_record = 1;
+        if ((ch == '\n') || (ch == '\r')) end_of_record = 1;
+        if ((ch == '\n') || (ch == '\r')) end_of_data = (rx_count == 0) ? 1 : 0;
+        }
+    } while ((rx_count <= 16) && (end_of_record == 0));
+    if (rx_count > 0) {
+      if (ch == ',')
+        printf(","); // ',' per CSV record
+      else
+        printf(".\n"); // newline delimiter
+
+      if (ch == ',')
+        sprintf(tx_buf,"%04x,", value);
+      else
+        sprintf(tx_buf,"%04x\n", value);
+
+      tx_buf[5]=0; // string zero terminate
+      
+      DataIO_puts((unsigned char*) tx_buf);
+//      do { /*tx process */
+//        if (DataIO_putc_ready()) {
+//          DataIO_putc(tx_buf[tx_count++]);
+//         }
+//      } while (tx_count < 5);
+    }
+  } while (end_of_data == 0); // outer record loop
+  
+  printf("** DATA FILE PROCESSING ** TEST PASSED **\n");
+  
+////  dataout = fopen("dataout","w");
+////  printf("file handle =,%08x\n",dataout);
+////  fputc(127, dataout);
+////  fclose(dataout);
+  
+  UartEndSimulation();
+  return 0;
+
+}

testcodes/dataio_tests/dataio_tests.hex

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testcodes/dataio_tests/makefile

+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+#            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+#                ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+#      SVN Information
+#
+#      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+#      Revision            : $Revision: 371321 $
+#
+#      Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+#  Configurations
+#
+# Choose the core instantiated, can be
+#  - CORTEX_M0
+#  - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR    = $(SOFTWARE_DIR)/cmsis
+CORE_DIR     = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  DEVICE_DIR   = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+  DEVICE_DIR   = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME     = dataio_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  USER_DEFINE    = -DCORTEX_M0PLUS
+else
+  USER_DEFINE    = -DCORTEX_M0
+endif
+
+DEPS_LIST       = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN      = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+  ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+    CPU_TYPE        = --cpu Cortex-M0plus
+  else
+    CPU_TYPE        = --cpu Cortex-M0
+  endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+  ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+    CPU_TYPE        = -mcpu=cortex-m0plus
+  else
+    CPU_TYPE        = -mcpu=cortex-m0
+  endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR  = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR  = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  STARTUP_FILE = startup_CMSDK_CM0plus
+  SYSTEM_FILE  = system_CMSDK_CM0plus
+else
+  STARTUP_FILE = startup_CMSDK_CM0
+  SYSTEM_FILE  = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+ARM_CC_OPTIONS   = -c -O3 -Ospace -I $(DEVICE_DIR)/Include  -I $(CORE_DIR) \
+		   -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_ASM_OPTIONS  = 
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+		   --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map  --info sizes
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS   += --bigend
+ ARM_ASM_OPTIONS  += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS   += --library_type=microlib
+ ARM_ASM_OPTIONS  += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS   += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC      = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS   += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst $(TESTNAME).bin
+
+$(TESTNAME).o :  $(TESTNAME).c $(DEPS_LIST)
+	armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+dataio_functions.o :  dataio_functions.c dataio_functions.h $(DEPS_LIST)
+	armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+	armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+	armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+	armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+	armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o  $@
+
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o dataio_functions.o retarget.o uart_stdout.o
+	armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o dataio_functions.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+	fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).bin : $(TESTNAME).ELF
+	fromelf --bin $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+	fromelf -c -d -e -s -z -v $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+	$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+		$(TESTNAME).c \
+		$(SOFTWARE_DIR)/common/retarget/retarget.c \
+		$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+		$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+		-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+        -I $(SOFTWARE_DIR)/common/retarget  \
+		-I $(SOFTWARE_DIR)/drivers \
+		-L $(LINKER_SCRIPT_PATH) \
+		-D__STACK_SIZE=0x200 \
+		-D__HEAP_SIZE=0x1000 \
+		$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+	# Generate disassembly code
+	$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+	# Generate binary file
+	$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+	# Generate hex file
+	$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+#       od -v -A n -t x1 --width=1  $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+	@echo "Please compile your project code and press ENTER when ready"
+	@read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+	# Generate hex file from binary
+	od -v -A n -t x1 --width=1  $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+	@rm -rf *.o
+	@if [ -e $(TESTNAME).hex ] ; then \
+	  rm -rf $(TESTNAME).hex ; \
+	fi
+	@if [ -e $(TESTNAME).lst ] ; then \
+	  rm -rf $(TESTNAME).lst ; \
+	fi
+	@if [ -e $(TESTNAME).ELF ] ; then \
+	  rm -rf $(TESTNAME).ELF ; \
+	fi
+	@if [ -e $(TESTNAME).bin ] ; then \
+	  rm -rf $(TESTNAME).bin ; \
+	fi
+	@rm -rf *.crf
+	@rm -rf *.plg
+	@rm -rf *.tra
+	@rm -rf *.htm
+	@rm -rf *.map
+	@rm -rf *.dep
+	@rm -rf *.d
+	@rm -rf *.lnp
+	@rm -rf *.bak
+	@rm -rf *.lst
+	@rm -rf *.axf
+	@rm -rf *.sct
+	@rm -rf *.__i
+	@rm -rf *._ia

testcodes/software_list.txt

@@ -17,3 +17,4 @@ apb_mux_tests
 memory_tests
 romtable_tests
 interrupt_demo
+dataio_tests

verif/tb/verilog/nanosoc_tb.v

@@ -92,7 +92,10 @@ localparam BE=0;
   localparam ADP_FILENAME="adp.cmd";
 `endif
 
+localparam DATA_IN_FILENAME="data_in.csv";
+localparam DATA_OUT_FILENAME="logs/data_out.csv";
 
+/*
 SROM_Ax32
   #(.ADDRWIDTH (8),
     .filename ("bootrom/hex/bootloader.hex"),
@@ -104,6 +107,7 @@ SROM_Ax32
     .SEL(1'b0),
     .RDATA( )
   );
+*/
 
 `ifdef SDF_SIM
 initial
@@ -334,20 +338,6 @@ extio8x4_axis_target u_extio8x4_axis_target
   );
 `endif
 
-/*
-  nanosoc_axi_stream_io_8_txd_from_file #(
-    .TXDFILENAME(ADP_FILENAME),
-//    .CODEFILENAME("null.hex"),
-    .FAST_LOAD(FAST_LOAD)
-  ) u_nanosoc_axi_stream_io_dat_txd_from_file (
-    .aclk       (CLK),
-    .aresetn    (NRST),
-    .txd8_ready (axis_rx1_tready),
-    .txd8_valid (axis_rx1_tvalid),
-    .txd8_data  (axis_rx1_tdata8)
-  );
-*/
-
   nanosoc_axi_stream_io_8_rxd_to_file#(
     .RXDFILENAME("logs/extadp_out.log"),
     .VERBOSE(0)
@@ -372,21 +362,29 @@ extio8x4_axis_target u_extio8x4_axis_target
     .AUXCTRL              ()
   );
 
+  nanosoc_axi_stream_io_8_txd_from_datafile #(
+    .TXDFILENAME(DATA_IN_FILENAME)
+  ) u_nanosoc_axi_stream_io_8_txd_from_datafile (
+    .aclk       (CLK),
+    .aresetn    (NRST),
+    .txd8_ready (axis_rx1_tready),
+    .txd8_valid (axis_rx1_tvalid),
+    .txd8_data  (axis_rx1_tdata8)
+  );
+
+
 
   nanosoc_axi_stream_io_8_rxd_to_file#(
-    .RXDFILENAME("logs/extdat_out.log")
+    .RXDFILENAME(DATA_OUT_FILENAME)
   ) u_nanosoc_axi_stream_io_extdata_8_rxd_to_file (
     .aclk         (CLK),
     .aresetn      (NRST),
     .eof_received ( ),
-    .rxd8_ready   ( ), //axis_tx1_tready),
-    .rxd8_valid   (axis_tx1_tvalid & axis_tx1_tready),
+    .rxd8_ready   (axis_tx1_tready),
+    .rxd8_valid   (axis_tx1_tvalid),
     .rxd8_data    (axis_tx1_tdata8)
   );
 
-assign axis_tx1_tready = axis_rx1_tready;
-assign axis_rx1_tvalid = axis_tx1_tvalid;
-assign axis_rx1_tdata8 = axis_tx1_tdata8;
 `endif
 
  // --------------------------------------------------------------------------------

verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_datafile.v

+//-----------------------------------------------------------------------------
+// 8-bit AXI-Stream File TX playback
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (c) 2023-25, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_axi_stream_io_8_txd_from_datafile
+  #(parameter TXDFILENAME = "data.txt",
+    parameter WAITSTATE = 0,
+    parameter VERBOSE = 0)
+  (
+  input  wire  aclk,
+  input  wire  aresetn,
+  input  wire  txd8_ready,
+  output wire  txd8_valid,
+  output wire  [7:0] txd8_data
+  );
+
+
+ //----------------------------------------------
+ //-- File I/O
+ //----------------------------------------------
+
+
+   integer        fd;       // channel descriptor for cmd file input
+   integer        ch;
+   integer        i;
+   
+`define EOF -1
+
+   reg       valid;
+   reg [7:0] data8;
+   reg       eot; // Ctrl-D encountered
+   
+   initial
+     begin
+       eot <= 1'b0;
+       valid <= 1'b0;
+//       $timeformat(-9, 0, " ns", 14);
+       fd= $fopen(TXDFILENAME,"r");
+       if (fd == 0)
+          $write("** %m : input file failed to open **\n");
+       else begin
+         @(posedge aresetn);
+         ch =  $fgetc(fd);
+         while ((ch != `EOF) && (!eot)) begin
+           @(posedge aclk);
+           data8 <= (ch & 8'hff);
+           valid <= 1'b1;
+           if (ch == 8'h04)
+               eot <= 1'b1;
+           @(posedge aclk);
+           while (txd8_ready == 1'b0)
+             @(posedge aclk);
+           valid <= 1'b0;
+           ch =  (eot) ? `EOF : $fgetc(fd);
+           for (i=0; i <  WAITSTATE; i=i+1)
+             @(posedge aclk);
+         end
+         $write("** %m : file closed after stream TX completed **\n");
+         $fclose(fd);
+         valid <= 1'b0;
+       end
+     end
+
+assign txd8_valid = valid;
+assign txd8_data = data8;
+
+endmodule

verif/trace/verilog/soclabs_axis8_capture.v

@@ -58,7 +58,6 @@ module soclabs_axis8_capture
   (
   input  wire       RESETn,              // Power on reset
   input  wire       CLK,                 // Clock (baud rate)
-  input  wire       RXD,                 // Received data
 
   output wire       RXD8_READY,
   input  wire       RXD8_VALID,
@@ -69,7 +68,6 @@ module soclabs_axis8_capture
   output wire [7:0] AUXCTRL);            // Auxiliary control
 
   reg [8:0]        rx_shift_reg;
-  wire [8:0]       nxt_rx_shift;
   reg [6:0]        string_length;
   reg [7:0]        tube_string [127:0];
   reg [7:0]        text_char;
@@ -104,20 +102,7 @@ assign RXD8_READY = rx_shift_reg[0]; // ready except for a cycle processing
      end
 
   // Receive shift register
-  assign nxt_rx_shift  = {RXD,rx_shift_reg[8:1]};
   assign char_received = (rx_shift_reg[0]==1'b0);
-/*
-  always @(posedge CLK or negedge RESETn)
-  begin
-    if (~RESETn)
-      rx_shift_reg <= {9{1'b0}};
-    else
-      if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
-        rx_shift_reg <= {9{1'b1}};
-      else
-        rx_shift_reg <= nxt_rx_shift;
-  end
-*/
 
 // ARM design wants valid char in rx_shift_reg[9:1]
 // and a zero in rx_shift_reg[0] to indicate valid start bit (so preset back to 1 after a clock cycle)