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SoCLabs
NanoSoC Tech
Commits
ecbda8ae
Commit
ecbda8ae
authored
5 months ago
by
dwf1m12
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extio synchronizers reset high to suppress spurious requests
parent
6b28a59e
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2
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2 changed files
extio8x4-axis/rtl/extio8x4_axis_initiator.v
+15
-8
15 additions, 8 deletions
extio8x4-axis/rtl/extio8x4_axis_initiator.v
extio8x4-axis/rtl/extio8x4_sync.v
+4
-3
4 additions, 3 deletions
extio8x4-axis/rtl/extio8x4_sync.v
with
19 additions
and
11 deletions
extio8x4-axis/rtl/extio8x4_axis_initiator.v
+
15
−
8
View file @
ecbda8ae
...
@@ -55,8 +55,12 @@ extio8x4_sync u_extio8x4_sync_ioack
...
@@ -55,8 +55,12 @@ extio8x4_sync u_extio8x4_sync_ioack
.
sig_s
(
ioack_s
)
.
sig_s
(
ioack_s
)
);
);
extio8x4_sync
u_extio8x4_sync_iodata0
// async status on iodata4 is active-low so preset synchronizers to avoid spurious requests
(
extio8x4_sync
#
(
.
RESET_VALUE
(
1'b1
)
)
u_extio8x4_sync_iodata0
(
.
clk
(
clk
),
.
clk
(
clk
),
.
resetn
(
resetn
),
.
resetn
(
resetn
),
.
testmode
(
testmode
),
.
testmode
(
testmode
),
...
@@ -64,8 +68,9 @@ extio8x4_sync u_extio8x4_sync_iodata0
...
@@ -64,8 +68,9 @@ extio8x4_sync u_extio8x4_sync_iodata0
.
sig_s
(
iodata4_s
[
0
])
.
sig_s
(
iodata4_s
[
0
])
);
);
extio8x4_sync
u_extio8x4_sync_iodata1
extio8x4_sync
#
(
(
.
RESET_VALUE
(
1'b1
)
)
u_extio8x4_sync_iodata1
(
.
clk
(
clk
),
.
clk
(
clk
),
.
resetn
(
resetn
),
.
resetn
(
resetn
),
.
testmode
(
testmode
),
.
testmode
(
testmode
),
...
@@ -73,8 +78,9 @@ extio8x4_sync u_extio8x4_sync_iodata1
...
@@ -73,8 +78,9 @@ extio8x4_sync u_extio8x4_sync_iodata1
.
sig_s
(
iodata4_s
[
1
])
.
sig_s
(
iodata4_s
[
1
])
);
);
extio8x4_sync
u_extio8x4_sync_iodata2
extio8x4_sync
#
(
(
.
RESET_VALUE
(
1'b1
)
)
u_extio8x4_sync_iodata2
(
.
clk
(
clk
),
.
clk
(
clk
),
.
resetn
(
resetn
),
.
resetn
(
resetn
),
.
testmode
(
testmode
),
.
testmode
(
testmode
),
...
@@ -82,8 +88,9 @@ extio8x4_sync u_extio8x4_sync_iodata2
...
@@ -82,8 +88,9 @@ extio8x4_sync u_extio8x4_sync_iodata2
.
sig_s
(
iodata4_s
[
2
])
.
sig_s
(
iodata4_s
[
2
])
);
);
extio8x4_sync
u_extio8x4_sync_iodata3
extio8x4_sync
#
(
(
.
RESET_VALUE
(
1'b1
)
)
u_extio8x4_sync_iodata3
(
.
clk
(
clk
),
.
clk
(
clk
),
.
resetn
(
resetn
),
.
resetn
(
resetn
),
.
testmode
(
testmode
),
.
testmode
(
testmode
),
...
...
This diff is collapsed.
Click to expand it.
extio8x4-axis/rtl/extio8x4_sync.v
+
4
−
3
View file @
ecbda8ae
...
@@ -10,8 +10,9 @@
...
@@ -10,8 +10,9 @@
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
module
extio8x4_sync
module
extio8x4_sync
#(
(
parameter
RESET_VALUE
=
1'b0
)(
input
wire
clk
,
input
wire
clk
,
input
wire
resetn
,
input
wire
resetn
,
input
wire
testmode
,
input
wire
testmode
,
...
@@ -24,7 +25,7 @@ reg [2:1] sig_r;
...
@@ -24,7 +25,7 @@ reg [2:1] sig_r;
always
@
(
posedge
clk
or
negedge
resetn
)
always
@
(
posedge
clk
or
negedge
resetn
)
begin
begin
if
(
!
resetn
)
if
(
!
resetn
)
sig_r
<=
2'b00
;
// default
sig_r
<=
{
2
{
RESET_VALUE
}}
;
// support active-low/high reset initial values
else
else
sig_r
<=
{
sig_r
[
1
],
sig_a
}
;
// shift left
sig_r
<=
{
sig_r
[
1
],
sig_a
}
;
// shift left
end
end
...
...
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