diff --git a/extio8x4-axis/rtl/extio8x4_axis_initiator.v b/extio8x4-axis/rtl/extio8x4_axis_initiator.v
index 5224cc78258ce237ea1ee95be23cb5289ab71118..2289a5b4e5b9b5b4ba98e18fb0bfcf8181915833 100644
--- a/extio8x4-axis/rtl/extio8x4_axis_initiator.v
+++ b/extio8x4-axis/rtl/extio8x4_axis_initiator.v
@@ -55,8 +55,12 @@ extio8x4_sync u_extio8x4_sync_ioack
   .sig_s(ioack_s)
   );
 
-extio8x4_sync u_extio8x4_sync_iodata0
-  (
+// async status on iodata4 is active-low so preset synchronizers to avoid spurious requests
+
+extio8x4_sync  # (
+  .RESET_VALUE(1'b1)
+  )
+  u_extio8x4_sync_iodata0 (
   .clk(clk),
   .resetn(resetn),
   .testmode(testmode),
@@ -64,8 +68,9 @@ extio8x4_sync u_extio8x4_sync_iodata0
   .sig_s(iodata4_s[0])
   );
 
-extio8x4_sync u_extio8x4_sync_iodata1
-  (
+extio8x4_sync  # (
+  .RESET_VALUE(1'b1)
+  ) u_extio8x4_sync_iodata1 (
   .clk(clk),
   .resetn(resetn),
   .testmode(testmode),
@@ -73,8 +78,9 @@ extio8x4_sync u_extio8x4_sync_iodata1
   .sig_s(iodata4_s[1])
   );
 
-extio8x4_sync u_extio8x4_sync_iodata2
-  (
+extio8x4_sync  # (
+  .RESET_VALUE(1'b1)
+  ) u_extio8x4_sync_iodata2 (
   .clk(clk),
   .resetn(resetn),
   .testmode(testmode),
@@ -82,8 +88,9 @@ extio8x4_sync u_extio8x4_sync_iodata2
   .sig_s(iodata4_s[2])
   );
 
-extio8x4_sync u_extio8x4_sync_iodata3
-  (
+extio8x4_sync   # (
+  .RESET_VALUE(1'b1)
+  ) u_extio8x4_sync_iodata3 (
   .clk(clk),
   .resetn(resetn),
   .testmode(testmode),
diff --git a/extio8x4-axis/rtl/extio8x4_sync.v b/extio8x4-axis/rtl/extio8x4_sync.v
index ed8d53f28636264d695cf0dad497b55c36182c20..55a03e10acebebcc065362c6b5fad4efa5761cc9 100644
--- a/extio8x4-axis/rtl/extio8x4_sync.v
+++ b/extio8x4-axis/rtl/extio8x4_sync.v
@@ -10,8 +10,9 @@
 // Copyright (c) 2024, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
-module extio8x4_sync
-  (
+module extio8x4_sync #(
+    parameter    RESET_VALUE = 1'b0
+  )(
   input  wire clk,
   input  wire resetn,
   input  wire testmode,
@@ -24,7 +25,7 @@ reg [2:1] sig_r;
 always @(posedge clk or negedge resetn)
 begin
   if (!resetn)
-    sig_r <= 2'b00; // default
+    sig_r <= {2{RESET_VALUE}}; // support active-low/high reset initial values
   else
     sig_r <= {sig_r[1], sig_a}; // shift left
 end