remove timescale directive from bus matrix build

...u/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr

...act/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml

...uilt/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml

...rilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v

...clabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v

.../built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v

...verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v

...log/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v

...uilt/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v

...uilt/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v

...uilt/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v

...ilt/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v

...log/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v