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Commit dc546576 authored by dwf1m12's avatar dwf1m12
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update FPGA build for ft1248-to-axi-stream functionality

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Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
+ 43
− 9
View file @ dc546576
......@@ -23,7 +23,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
......@@ -136,7 +136,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d48af1db</spirit:value>
<spirit:value>07d8b26e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -152,7 +152,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d48af1db</spirit:value>
<spirit:value>07d8b26e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -400,7 +400,7 @@
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_74b5137e</spirit:name>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
......@@ -419,7 +419,7 @@
<spirit:file>
<spirit:name>hdl/ft1248x1_to_axi_streamio_v1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_dbb92f62</spirit:userFileType>
<spirit:userFileType>CHECKSUM_1d919ea1</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -493,8 +493,8 @@
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>ft1248x1_to_axi_streamio_v1.0</xilinx:displayName>
<xilinx:coreRevision>5</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2023-02-20T10:15:53Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>8</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2023-02-26T14:27:06Z</xilinx:coreCreationDateTime>
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......@@ -581,12 +581,46 @@
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<xilinx:packagingInfo>
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......
Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
+ 2
− 0
View file @ dc546576
......@@ -13,6 +13,7 @@ module SYNCHRONIZER_EDGES (
,input wire reset_n_i
,input wire asyn_i
,output wire syn_o
,output wire syn_del_o
,output wire posedge_o
,output wire negedge_o
);
......@@ -34,6 +35,7 @@ reg sync_stage3;
end
assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
assign syn_del_o = (testmode_i) ? asyn_i : sync_stage3;
assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
......
Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
+ 27
− 14
View file @ dc546576
......@@ -35,9 +35,6 @@
input wire ft_miosio_i,
output wire ft_miosio_o,
output wire ft_miosio_z,
// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO
//
// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
input wire aclk, // external primary clock
input wire aresetn, // external reset (active low)
......@@ -59,8 +56,7 @@ wire ft_clk_rising;
wire ft_clk_falling;
wire ft_ssn;
//wire ft_ssn_rising;
//wire ft_ssn_falling;
wire ft_miosio_i_del;
SYNCHRONIZER_EDGES u_sync_ft_clk (
.testmode_i(1'b0),
......@@ -68,6 +64,7 @@ SYNCHRONIZER_EDGES u_sync_ft_clk (
.reset_n_i(aresetn),
.asyn_i(ft_clk_i),
.syn_o(),
.syn_del_o(),
.posedge_o(ft_clk_rising),
.negedge_o(ft_clk_falling)
);
......@@ -78,6 +75,18 @@ SYNCHRONIZER_EDGES u_sync_ft_ssn (
.reset_n_i(aresetn),
.asyn_i(ft_ssn_i),
.syn_o(ft_ssn),
.syn_del_o(),
.posedge_o( ),
.negedge_o( )
);
SYNCHRONIZER_EDGES u_sync_ft_din (
.testmode_i(1'b0),
.clk_i(aclk),
.reset_n_i(aresetn),
.asyn_i(ft_miosio_i),
.syn_o( ),
.syn_del_o(ft_miosio_i_del),
.posedge_o( ),
.negedge_o( )
);
......@@ -130,7 +139,7 @@ wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0]
wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
// tristate enable for miosio (deselected status or serialized data for read command)
wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
assign ft_miosio_z = !ft_miosio_e;
// capture (ft_cmd_txd) serial data out on falling edge of clock
......@@ -142,7 +151,7 @@ always @(posedge aclk or negedge aresetn)
else if (ft_ssn) // sync reset
rxd_sr <= 8'b00000000;
else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
rxd_sr <= {ft_miosio_i, rxd_sr[7:1]};
rxd_sr <= {ft_miosio_i_del, rxd_sr[7:1]};
// AXI STREAM handshake interfaces
// TX stream delivers valid FT1248 read data transfer
......@@ -154,7 +163,7 @@ always @(posedge aclk or negedge aresetn)
else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
txstream[8] <= 1'b0;
else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]};
txstream[8:0] <= {1'b1, ft_miosio_i_del, rxd_sr[7:1]};
assign txd_tvalid_o = txstream[8];
assign txd_tdata8_o = txstream[7:0];
......@@ -163,6 +172,8 @@ assign txd_tdata8_o = txstream[7:0];
// AXI STREAM handshake interfaces
// RX stream accepts 8-bit data to transfer over FT1248 channel
// 8-bit write port with extra top-bit used as valid qualifer
/*
reg [8:0] rxstream;
always @(posedge aclk or negedge aresetn)
if (!aresetn)
......@@ -172,28 +183,30 @@ always @(posedge aclk or negedge aresetn)
else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
rxstream[8] <= 1'b0;
assign rxd_tready_o = !rxstream[8]; // ready until loaded
*/
// shift TXD on rising edge of clock
reg [7:0] txd_sr;
reg [8:0] txd_sr;
// rewrite for clocked
always @(posedge aclk or negedge aresetn)
if (!aresetn)
txd_sr <= 8'b00000000;
else if (ft_ssn) // sync reset
txd_sr <= 8'b00000000;
else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111))
txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000;
else if (ft_clk_falling & ft_cmd_rxd & rxd_tvalid_i & (ft_state == 5'b00111))
txd_sr <= rxd_tdata8_i;
else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
txd_sr <= {1'b0,txd_sr[7:1]};
assign rxd_tready_o = (ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01110)); // hold until final shift
//FT1248 FIFO status signals
// ft_miso_o reflects TXF when deselected
assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0];
assign ft_miosio_o = (ft_ssn_i) ? txstream[8] : txd_sr[0];
// ft_miso_o reflects RXE when deselected
assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
//assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
assign ft_miso_o = (ft_ssn_i) ? !rxd_tvalid_i : ((ft_state == 5'b00111) & ((ft_cmd_txd) ? txstream[8]: !rxd_tvalid_i));
endmodule
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